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DRV8461SPWPR 数据表(PDF) 51 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 51 Page - Texas Instruments |
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51 / 117 page  Table 7-26. Standstill fall time and delay time Parameter Description TSTSL_FALL[3:0] Controls the time taken by the current to reduce from TRQ_DAC to ISTSL after TSTSL_DLY time has elapsed. For each TSTSL_FALL, TRQ_DAC will fall by 1b til the current reaches ISTSL. Total fall time = (TRQ_DAC - ISTSL) * fall time for each current step. • 0000b: fall time = 0 • 0001b: fall time for each current step = 1 ms • ............ • 0100b: fall time for each current step = 4 ms (default) • ............ • 1111b: fall time for each current step = 15 ms TSTSL_DLY[5:0] Controls the delay between last STEP pulse and activation of standstill power saving mode. • 000000b: Reserved • 000001b: Delay = 1 x 16 ms = 16 ms • ............ • 000100b: Delay = 4 x 16 ms = 64 ms (default) • ............ • 111111b: Delay = 63 x 16 ms = 1.008 s Note • If ISTSL has to be changed while the device is in standstill power saving mode, first cycle the EN_STSL bit from 1b to 0b and then back to 1b. • When auto-torque is enabled, program ISTSL between ATQ_TRQ_MAX and ATQ_TRQ_MIN. 7.3.14 Charge Pump A charge pump is integrated to supply the high-side N-channel MOSFET gate-drive voltage. The charge pump requires a capacitor between the VM and VCP pins to act as the storage capacitor. Additionally a ceramic capacitor is required between the CPH and CPL pins to act as the flying capacitor. VM VCP 1 μF VM CPH Charge Pump Control VM CPL 0.1 μF Figure 7-30. Charge Pump Block Diagram www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DRV8461 |
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