DRV8461SPWPR datasheet(62/117 Pages) TI

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Table 7-27. Open-load Detection Time (continued)

Interface

OL_T

Maximum tOL (ms)

SPI interface

00b

01b (default)

10b

120

Once the open-load fault is detected -

• nFAULT is pulled low.

• If the device is operating with SPI interface -

– OL and FAULT bits are latched 1b

– If the OL_A bit is 1b, it indicates an open load fault in winding A, between AOUT1 and AOUT2.

– An open load fault between BOUT1 and BOUT2 causes the OL_B bit to become 1b.

When the open-load condition is removed, the behavior depends on whether the device is configured with H/W

interface or SPI interface.

When the device is configured with H/W interface and open-load condition is removed:

• If the ENABLE pin is logic HIGH, nFAULT is released immediately.

• If the ENABLE pin is Hi-Z, nFAULT is released after a nSLEEP reset pulse has been applied.

When the device is configured with SPI interface and open-load condition is removed:

• If the OL_MODE bit is 1b, nFAULT is released immediately. OL bit in FAULT register and OL_X bits in DIAG2

reset pulse.

• If the OL_MODE bit is 0b, nFAULT and the fault bits are released after a clear faults command is issued

either via the CLR_FLT bit or an nSLEEP reset pulse.

The open-load fault also clears when the device is power cycled or comes out of sleep mode.

DRV8461

SLOSE98 – DECEMBER 2022

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