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DRV8461SPWPR 数据表(PDF) 9 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 9 Page - Texas Instruments |
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9 / 117 page  Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIL Input logic-low voltage 0 0.6 V VIH Input logic-high voltage (all pins except DECAY1) 1.5 5.5 V VIH_DECAY1 Input logic-high voltage (DECAY1 pin) 2.7 5.5 V VHYS Input logic hysteresis (all pins except nSLEEP) 100 mV VHYS_SLEEP nSLEEP logic hysteresis 300 mV IIL Input logic-low current (all pins except nSCS) VIN = 0 V –1 1 μA IIL_nSCS nSCS logic-low current nSCS = 0V 8 12 μA IIH Input logic-high current (all pins except nSCS, 200k internal pull- down resistance) VIN = DVDD 50 μA IIH_nSCS nSCS logic-high current nSCS = DVDD 0.1 μA TRI-LEVEL INPUTS (M0, DECAY0, ENABLE) VI1_tri Input logic-low voltage Tied to GND 0 0.6 V VI2_tri Input Hi-Z voltage Hi-Z 1.8 2 2.2 V VI3_tri Input logic-high voltage Tied to DVDD 2.7 5.5 V IO_tri Output pull-up current 10.5 μA QUAD-LEVEL INPUTS (M1, TOFF) VI1_quad Input logic-low voltage Tied to GND 0 0.6 V VI2_quad Input second level voltage 330kΩ ± 5% to GND 1 1.25 1.4 V VI3_quad Input Hi-Z voltage Hi-Z 1.8 2 2.2 V VI4_quad Input logic-high voltage Tied to DVDD 2.7 5.5 V IO_quad Output pull-up current 10.5 μA PUSH-PULL OUTPUT (SDO) RPD,SDO Internal pull-down resistance 5mA load, with respect to GND 30 60 Ω RPU,SDO Internal pull-up resistance 5mA load, with respect to VCC 60 110 Ω ISDO SDO Leakage Current(1) VVM > 6 V, SDO = VCC and 0V -2.5 2.5 μA CONTROL OUTPUTS (nFAULT, nHOME) VOL Output logic-low voltage IO = 5 mA 0.35 V IOH Output logic-high leakage -1 1 μA MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) RDS(ONH) High-side FET on resistance TJ = 25 °C, IO = -3 A 150 175 mΩ TJ = 125 °C, IO = -3 A 225 285 mΩ TJ = 150 °C, IO = -3 A 255 325 mΩ www.ti.com DRV8461 SLOSE98 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV8461 |
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