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DRV8461SPWPR 数据表(PDF) 76 Page - Texas Instruments |
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DRV8461SPWPR 数据表(HTML) 76 Page - Texas Instruments |
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76 / 117 page  Table 7-40. Control Registers Summary Table (continued) Address Register Name Section 0x0B CTRL8 Go 0x0C CTRL9 Go 0x0D CTRL10 Go 0x0E CTRL11 Go 0x0F CTRL12 Go 0x1A CTRL13 Go 0x3C CTRL14 Go 7.5.2.1 CTRL1 (address = 0x04) [Default = 0Fh] CTRL1 is shown in Figure 7-60 and described in Table 7-41. Read/Write Return to the Register Maps Table Figure 7-60. CTRL1 Control Register 7 6 5 4 3 2 1 0 EN_OUT SR IDX_RST TOFF [1:0] DECAY [2:0] R/W-0b R/W-0b R/W-0b R/W-01b R/W-111b Table 7-41. CTRL1 Control Register Field Descriptions Bit Field Type Default Description 7 EN_OUT R/W 0b 0b = All outputs are disabled 1b = All outputs are enabled 6 SR R/W 0b 0b = Output rise/fall time 140 ns 1b = Output rise/fall time 70 ns 5 IDX_RST R/W 0b When this bit is 1b, it resets the indexer to 45° electrical angle, but the contents of the memory map registers will not change. 4-3 TOFF [1:0] R/W 01b • 00b = 9 µs • 01b = 19 µs • 10b = 27 µs • 11b = 35 µs 2-0 DECAY [2:0] R/W 111b • 000b = Slow decay • 100b = Mixed 30% decay • 101b = Mixed 60% decay • 110b = Smart tune Dynamic Decay • 111b = Smart tune Ripple Control • 001b, 010b, 011b = Reserved 7.5.2.2 CTRL2 (address = 0x05) [Default = 06h] CTRL2 is shown in Figure 7-61 and described in Table 7-42. Read/Write Return to the Register Maps Table Figure 7-61. CTRL2 Control Register 7 6 5 4 3 2 1 0 DIR STEP SPI_DIR SPI_STEP MICROSTEP_MODE [3:0] DRV8461 SLOSE98 – DECEMBER 2022 www.ti.com 76 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8461 |
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