DRV8461SPWPR datasheet(52/117 Pages) TI

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7.3.15 Linear Voltage Regulator

A linear voltage regulator is integrated within the device. When the VCC pin is connected to DVDD, the DVDD

regulator provides power to the low-side gate driver and all the internal circuits. For proper operation, bypass the

DVDD pin to GND using a 1 μF ceramic capacitor. The DVDD output is nominally 5 V.

1 μF

–

DVDD

5 V

Figure 7-31. Linear Voltage Regulator Block Diagram

If a digital input must be tied permanently high, tying the input to the DVDD pin instead of an external regulator

is preferred. This method saves power when the VM pin is not applied or in sleep mode: the DVDD regulator is

disabled and current does not flow through the input pulldown resistors. For reference, logic level inputs have a

typical pulldown of 200 kΩ.

The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.

7.3.16 VCC Voltage Supply

An external voltage can be applied to the VCC pin to power the internal logic circuitry. The voltage on the VCC

pin should be between 3.05V and 5.5V and should be well regulated. When an external supply is not available,

VCC pin must be connected to the DVDD pin of the device.

When powered by the VCC, the internal logic blocks do not consume power from the VM supply rail - thereby

reducing the power loss in the DRV8461. This is highly beneficial in high voltage applications, and when thermal

conditions are critical. Bypass the VCC pin to ground using a 0.1 μF ceramic capacitor.

7.3.17 Logic Level, Tri-Level and Quad-Level Pin Diagrams

Figure 7-32 shows the input structure for M0, DECAY0 and ENABLE pins.

Figure 7-32. Tri-Level Input Pin Diagram

Figure 7-33 shows the input structure for M1 and TOFF pins.

DRV8461

SLOSE98 – DECEMBER 2022

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DRV8461SPWPR 数据表(PDF) 52 Page - Texas Instruments