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DRA821U4...ALM 数据表(PDF) 105 Page - Texas Instruments

部件名 DRA821U4...ALM
功能描述  DRA821 Jacinto™ Processors
PDF  252 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DRA821U4...ALM 数据表(HTML) 105 Page - Texas Instruments

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7.6.9 SERDES Electrical Characteristics
Note
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base
Specification Revision 4.0, September 27, 2017.
This Device imposes an additional limit on SERDES REFCLK when used in Input mode with
internal termination enabled, as described by parameter VREFCLK_TERM in Table 7-2, SERDES
REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled
before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External
termination should always be enabled on the source side.
Table 7-2. SERDES REFCLK Electrical Characteristics
Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
BALL NAMES in Mode 0: SERDES0_REFCLK_P, SERDES0_REFCLK_N
BALL NUMBERS:AA9 / AA8
VREFCLK_TER
M
Single ended voltage threshold at the reference clock
pin when internal termination is enabled
400
mV
RTERM
Internal termination
40
50
62.5
Ω
Note
The SerDes USB interface is compliant with the USB3.1 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision
1.0 , July 26, 2013.
Note
The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3
Clause 70.
Note
The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47.
Note
The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2.
Note
USXGMII supports IEEE 802.3 TX and RX electrical characteristics of Clause 72-7 and Annex 69B.
IEEE 802.3 Tables 72-7 and 72-8 are not required by USXGMII since these tables are associated with
training (Clause 72-6), which is not a requirement of USXGMII.
The pre, main, and post cursors should be set by using BER sweeps.
Note
The XFI interface electrical characteristics are compliant with the INF-8077_XFP_XFI_10Gbps_1X
specification revision 4.5, August 31, 2005.
www.ti.com
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: DRA821U-Q1



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