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STR720 数据表(PDF) 208 Page - STMicroelectronics

部件名 STR720
功能描述  ARM720T 16/32-BIT MCU WITH 16K RAM, USB, CAN, 3 TIMERS, ADC, 6 COMMUNICATIONS INTERFACES
PDF  401 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STR720 数据表(HTML) 208 Page - STMicroelectronics

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STR720 - CONTROLLER AREA NETWORK (CAN)
208/401
18.4.8
Basic Mode
The CAN Core can be set in Basic Mode by programming the Test Register bit Basic to one.
In this mode, the CAN Peripheral runs without the Message RAM.
The IF1 Registers are used as Transmit Buffer. The transmission of the contents of the IF1
Registers are requested by writing the Busy bit of the IF1 Command Request Register to one.
The IF1 Registers are locked while the Busy bit is set. The Busy bit indicates that the
transmission is pending.
As soon the CAN bus is idle, the IF1 Registers are loaded into the shift register of the CAN
Core and the transmission is started. When the transmission has been completed, the Busy
bit is reset and the locked IF1 Registers are released.
A pending transmission can be aborted at any time by resetting the Busy bit in the IF1
Command Request Register while the IF1 Registers are locked. If the CPU has reset the
Busy bit, a possible retransmission in case of lost arbitration or in case of an error is disabled.
The IF2 Registers are used as a Receive Buffer. After the reception of a message the
contents of the shift register is stored into the IF2 Registers, without any acceptance filtering.
Additionally, the actual contents of the shift register can be monitored during the message
transfer. Each time a read Message Object is initiated by writing the Busy bit of the IF2
Command Request Register to one, the contents of the shift register are stored in the IF2
Registers.
In Basic Mode, the evaluation of all Message Object related control and status bits and the
control bits of the IFn Command Mask Registers are turned off. The message number of the
Command request registers is not evaluated. The NewDat and MsgLst bits in the IF2
Message Control Register retain their function, DLC3-0 indicate the received DLC, and the
other control bits are read as ‘0’.
18.4.9
Software Control of CAN_TX Pin
Four output functions are available for the CAN transmit pin, CAN_TX. In addition to its default
function (serial data output), the CAN transmit pin can drive the CAN Sample Point signal to
monitor CAN_Core’s bit timing and it can drive constant dominant or recessive values. The
latter two functions, combined with the readable CAN receive pin CAN_RX, can be used to
check the physical layer of the CAN bus.
The output mode for the CAN_TX pin is selected by programming the Tx1 and Tx0 bits of the
CAN Test Register.
The three test functions of the CAN_TX pin interfere with all CAN protocol functions. CAN_TX
must be left in its default function when CAN message transfer or any of the test modes (Loop
Back Mode, Silent Mode, or Basic Mode) are selected.
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