H5GQ2H24AFR-R0C datasheet(137/172 Pages) HYNIX

137 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

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Rev. 1.2 /Nov. 2011

137

H5GQ2H24AFR

PARAMETER a, b

SYMBOL

6.0Gbps

UNIT

NOTES

MIN

MAX

WCK2CK Timings

WCK stop to MRS delay for entering WCK2CK training

tWCK2MRS

MRS to WCK restart delay after entering WCK2CK training

tMRSTWCK

WCK start to WCK phase movement delay

tWCK2TR

tCK

WCK phase change to phase detector out delay

tWCK2PH

WCK Clock high-level width during WCK2CK training

tWCKHTR

0.43

0.57

tWCK

k,l,r

WCK Clock low-level width during WCK2CK training

tWCKLTR

0.43

0.57

tWCK

k,l,r

WCK2CK offset when zero offset at

phase detector or at pins

PLL on;MR6A0=0

(at phase detector)

tWCK2CKPIN

-0.2

0.2

PLL on;MR6A0=1

(at pins)

-0.2

0.2

PLL off;MR6A0=0

(at phase detector)

-0.2

0.2

PLL off;MR6A0=1

(at pins)

-0.2

0.2

WCK2CK phase offset upon

WCK2CK training exit

MR6A0=0

(at phase detector)

tWCK2CKSYNC

-0.25

0.25

tCK

MR6A0=1

(at pins)

-0.25

0.25

WCK2CK phase offset

MR6A0=0

(at phase detector)

tWCK2CK

-0.4

0.4

tCK

MR6A0=1

(at pins)

-0.4

0.4

PLL Input and Output Timings

WCK to DQ/DBI# offset for input

data

PLL on

tWCK2DQI

0.7

1.7

PLL off

0.7

1.7

WCK to DQ/DBI#/EDC/ offset for

output data

PLL on

tWCK2DQO

1.1

2.2

w,x

PLL off

1.1

2.2

DQ/DBI# input pulse width

tDIPW

0.15

y,z,aa

Table 44. AC Timings (@1.5V)

H5GQ2H24AFR-R0C 数据表(PDF) 137 Page - Hynix Semiconductor

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H5GQ2H24AFR-R0C 数据表(PDF) 137 Page - Hynix Semiconductor

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