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H5GQ2H24AFR-R0C 数据表(PDF) 144 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 144 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
144
H5GQ2H24AFR
PARAMETER a, b
SYMBOL
5.0Gbps
4.0Gbps
UNIT
NOTES
MIN
MAX
MIN
MAX
LDFF to LDFF command cycle time
tLTLTR
4
-
4
-
tCK
LDFF(111) to LDFF command cycle time
tLTL7TR
4
-
4
-
tCK
ao
LDFF(111) to RDTR command cycle delay
tLTRTR
4
-
4
-
tCK
READ or RDTR to LDFF command delay
tRDTLT
4
-
4
-
tCK
WRITE to LDFF command delay
tWRTLT
WL+5
-
WL+5
-
tCK
WRTR to RDTR command delay
tWTRTR
WL+
BL/4+1
-tWLmin
-
WL+
BL/4+1
-tWLmin
-tCK
ay
WRITE to WRTR command delay
tWRWTR
WL+tCRCWL+2
-
WL+tCRCWL+
2
-tCK
Internal WRITE to READ command delay same bank
group
tWTRL
1*tCK + 5ns
-
1*tCK + 5ns
-
ns
af
Internal WRITE to READ command delay different
bank groups
tWTRS
1*tCK + 5ns
-
1*tCK + 5ns
-
ns
ag
READ or RDTR to WRITE or WRTR command
delay
tRTW
[CLmrs+(BL/4)+2-
WLmrs]*tCK
-
[CLmrs+(BL/4)+2-
WLmrs]*tCK
-tCK
ap
Write Latency
tWL
3
7
3
7
tCK
aq
Power-Down and Refresh Timings
CKE# min high and low pulse width
tCKE
12
-
10
-
tCK
Valid CK Clock required after self refresh entry
tCKSRE
12
-
10
-
tCK
Valid CK Clock required before self refresh exit
tCKSRX
12
-
10
-
tCK
READ to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay
tRDSRE
CL+2tCK
-
CL+2tCK
-
tCK
ar
WRITE to SELF REFRESH ENTRY or POWER
DOWN ENTRY command delay
tWRSRE
WL+ BL/4 + 1tck +
Max(tDAL,
CRCWL+2tck)
-
WL+ BL/4 + 1tck
+ Max(tDAL,
CRCWL+2tck)
-tCK
as
REFRESH command period
tRFC
65
-
65
-
ns
Exit self refresh to non-READ/WRITE command
delay
tXSNRW
tRFC
-
tRFC
-
ns
Exit self refresh to READ/WRITE command delay
tXSRW
tRFC+
tRCD
-
tRFC+
tRCD
-tCK
at
Refresh period
tREF
-
32
-
32
ms
Average periodic refresh
interval
8k rows
tREFI
-3.9
-
3.9
us
au
16k rows
-
1.9
-
1.9
Min Power down entry to exit time
tPD
12
10
tCK
Table 44. AC Timings (@1.5V)



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