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H5GQ2H24AFR-R0C 数据表(PDF) 148 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 148 Page - Hynix Semiconductor |
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148 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 148 H5GQ2H24AFR PARAMETER a, b SYMBOL 5.0Gbps 4.0Gbps UNIT NOTES MIN MAX MIN MAX DQ/DBI# data input valid window PLL on tDIVW 0.15 - 0.17 - ns y,z,ab PLL off 0.15 - 0.17 - DQ/DBI# input skew within double byte tDQDQI -0.1 0.1 -0.1 0.1 ns ac DQ/DBI#/EDC output skew within double byte tDQDQO -0.125 0.125 -0.125 0.125 ns ad Row Access Timings Active to Active command period tRC 48 - 48 - ns Active to PRECHARGE command period tRAS 32 9*tREFI 32 9*tREFI ns ae Active to READ command delay tRCDRD 18 - 18 - ns Active to WRITE command delay tRCDWR 14 - 14 - ns Active to RDTR command delay tRCDRTR 16 - 16 - ns Active to WRTR command delay tRCDWTR 14 - 14 - ns Active to LDFF command delay tRCDLTR 14 - 14 - ns REFRESH to RDTR or WRTR command delay tREFTR 14 - 14 - ns Active bank A to Active bank B command delay same bank group tRRDL 7 - 7 - ns af Active bank A to Active bank B command delay different bank groups tRRDS 7 - 7 - ns ag Four bank activate window tFAW 30 - 30 - ns ah Thirty two bank activate window t32AW 245 - 245 - ns ai READ to PRECHARGE command delay same bank with bank groups enabled tRTPL 2 - 2 - tCK aj READ to PRECHARGE command delay same bank with bank groups disabled tRTPS 2 - 2 - tCK ak PRECHARGE to PRECHARGE command delay tPPD 1 - 1 - ns PRECHARGE command period tRP 16 - 16 - ns WRITE recovery time tWR 16 - 16 - ns Auto precharge write recovery + precharge time tDAL 32 - 32 - ns al Column Access Timings RD/WR bank A to RD/WR bank B command delay same bank group tCCDL 3 - 3 - tCK af,am RD/WR bank A to RD/WR bank B command delay different bank groups tCCDS 2 - 2 - tCK ag,an Table 44. AC Timings (@1.35V) |
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