H5GQ2H24AFR-R0C datasheet(151/172 Pages) HYNIX

151 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

151

H5GQ2H24AFR

l. The phase relationship between WCK/WCK# and CK/CK# clocks must meet the tWCK2CK specification.

m. Command and address input timings are referenced to VREFC.

n. Command and address input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIHA(AC)

or VILA(AC).

o. Command and address input pulse widths are design targets. The value will be characterized but not tested on each device.

p. Address input timings are only valid with ABI beging enabled and a maximum of 4 address input driven LOW.

q. Parameter may be specified as a combination of tCK and ns.

r. Parameters tWCKHTR and tWCKLTR specify the max. allowed WCK clock-to-clock phase shift during WCK2CK training. For READ and WRITE

bursts use tWCKH and tWCKL.

s. Parameter tWCK2CKPIN defines the WCK2CK phase offset range at the CK and WCK pins for ideal (phase=0 °) clock alignment at the

GDDR5 SGRAM’s phase detector (when the alignment point in MR6, bit A0 is set to “at phase detector”), or at the WCK and CK pins (when the

alignment in MR6, bit A0 is set to “at pins”). The minimum and maximum values could be negative or positive numbers, depending on the selected

WCK2CK alignment point, PLL-on or PLL-off mode and design implementation.

t. Parameter tWCK2CKSYNC defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase

detector (when the alignment point in MR6, bit A0 is set to “at the phase detector”), or at the WCK and CK pins (when the alignment point

in MR6, bit A0 is set to “at pins”), where the internal logic synchronizes the CK and WCK clocks; it is expected to be a fraction of tWCK2CK.

u. Parameter tWCK2CK defines the max. phase offset from the ideal (phase = 0 °) clock alignment at the GDDR5 SGRAM’s phase detector

(when the alignment point in MR6, bit A0 is set to “at phase detector”) or at the WCK and CK pins (when the alignment point in MR6, bit A0 is set to

“at pins”), for stable device operation.

v. Parameter tWCK2DQI defines the WCK to DQ/DBI# time delay range for WRITEs for PLL-on and PLL-off mode. The minimum and maximum values

could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.

Data training is required to determine the actual tWCK2DQI value for reliable WRITE operation.

w. Parameter tWCK2DQO defines the WCK to DQ/DBI# time delay range for READs for PLL-on and PLL-off mode. The minimum and maxium values

could be negative or positive numbers, depending on design implementation and PLL-on or PLL-off mode. They also vary across PVT.

Data training is required to determind the actual tWCK2DQO value for reliable READ operation.

x. Outputs measured with equivalent load terminated with 60 Ohms to VDDQ

y. DQ/DBI# input timings are valid only with DBI being enabled and a maximum of 4 data inputs per byte driven LOW.

z. Data input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC).

aa. The data input pulse width, tDIPW, defines the minimum positive or negative input pulse width for any worst-case channel required for proper

propagation of an external signal to the receiver. tDIPW is measured at the pins. tDIPW is independent of the PLL mode.

In general tDIPW is larger than tDIVW

ab. The data input valid width, tDIVW, defines the time region where input data must be valid for reliable data capture at the receiver for any one worst

case channel. It accounts for jitter between data and clock at the latching point introduced in the path between DARM pads and the latching point.

Any additional jitter introduced into the source signals (e.g. within the system before the DRAM pad) must be accounted for in the final timing

budget together with the chosen PLL mode and bandwidth. tDIVW is measured at the pins. tDIVW is defined for PLL off and on mode separately.

In the case of PLL on, tDIVW must be specified for each supported bandwidth. In general, tDIVW is smaller than tDIPW.

ac. tDQDQI defines the maximum skew among all DQ/DBI# inputs of a double byte (when configured to ×32 mode) or a single byte (when

configured to ×16 mode) under worst case conditions. Parameter tWCK2DQI defines the mean value of the earliest and latest DQ/DBI# pin,

tDQDQI(min) the negative offset to tWCK2DQI for the earliest DQ/DBI# pin and tDQDQI(max) the positive offset to tWCK2DQI for the latest

DQ/DBI# pin.

ad. tDQDQO defines the maximum skew among all DQ/DBI# outputs of a double byte (when configured to ×32mode) or a single byte (when

configured to ×16 mode) under worst case conditions. Parameter tWCK2DQO defines the mean value of of the earliest and latest DQ/DBI#

/EDC pin, tDQDQO(min) the negative offset to tWCK2DQO for earliest DQ/DBI#/EDC pin and tDQDQO(max) the positive offset to tWCK2DQO

for the latest DQ/DBI#/EDC pin.

ae. For READs and WRITEs with AUTO PRECHARGE enabled the device will hold off the internal PRECHARGE until tRAS(min) has been satisfied.

af. Parameter applies when bank groups are enabled and consecutive commands access the same bank group.

ag. Parameter applies when bank groups are disabled or consecutive commands access different bank group.

ah. Not more than 4 ACTIVE commands are allowed within period.

ai. Not more than 32 ACTIVE commands are allowed within t32AW period. The parameter need not to be specified in case t32AW(min) would not be

greater than 8*tFAW(min).

aj. Parameter applies when bank groups are enabled and READ and PRECHARGE commands access the same bank.

ak. Parameter applies when bank groups are disabled or READ and PRECHARGE commands access the same bank.

al. tDAL = (tWR/tCK) + ( tRP/tCK). For each of the terms, if not already an integer, round up to the next integer.

am. tCCDL is either for gapless consecutive READ or gapless consecutive WRITE commands

an. tCCDS is either for gapless consecutive READ or RDTR (any combination), gapless consecutive WRITE, or gapless consecutive WRTR commands.

ao. The min. value does not exceed 8 tCK

ap. tRTW is not a device limit but determined by the system bus turnaround time. The difference between tWCK2DQO and tWCK2DQI shall be considered

in the calculation of the bus turnaround time.

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