H5GQ2H24AFR-R0C datasheet(152/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

152

H5GQ2H24AFR

aq. The WRITE latency WLmrs cna be set to 3 to 7 clocks. When the WRITE latency is set to small values (3 ~ 4 clocks), the input buffers are always on,

reducing the latency but adding power. When the WRITE latency is set to larger values (5 ~ 7 clocks), the input buffers are turned on with the WRITE

command, thus saving power.

ar. Read data including CRC data must have been clocked out before entering self refresh or power down mode.

as. Write data must have been written to the memory core and CRC data must have been clocked out before entering self refresh or power down mode.

at. Time for WCK2CK training and data training not included.

au. A maximum of 8 consecutive REFRESH commands can be posted to a GDDR5 SGRAM device, meaning that the maximum absolute interval

between any REFRESH command and the next REFRESH command is 9*tREFI.

av. Replaces parameter tLK when PLL Fast Lock has been neabled prior to the PLL enable or reset.

aw. Replaces parameter tLK when PLL Standby has been enabed and the WCK clock frequency has not charged while in standby mode.

ax. The PLL standby time tSTDBY ismeasured from self refresh entry until after self refresh exit a subsequent PLL reset is given (with PLL Standby

enabled)

ay.

tWTRTR is Internal WRTR to External RDTR command delay.

In case, External WRTR to External RDTR command delay time is “WL+(WL+BL/4+1‐tWLmin)”.

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