H5GQ2H24AFR-R0C datasheet(150/172 Pages) HYNIX

150 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

150

H5GQ2H24AFR

PARAMETER a, b

SYMBOL

5.0Gbps

4.0Gbps

UNIT

NOTES

MIN

MAX

MIN

MAX

NOP/DESELECT commands required upon power-

down and self refresh entry

tCPDED

2-2-

tCK

Power down exit time

tXPN

tCK

Miscellaneous Timings

MODE REGISTER SET command period

tMRD

PLL enabled to PLL lock delay

tLK

5000

tCK

PLL standby time

tSTDBTY

TBD

Required time for duty cycle corrector (DCC)

tDCC

1300

tCK

DVS voltage stabilization time

tVS

TBD

REFRESH to calibration update complete delay

tKO

Active termination setup time

tATS

Active termination hold time

tATH

READ to data out delay in address training mode

tADR

0.5*tCK+

tCK

Address training exit to DQ in ODT state delay

tADZ

0.5*tCK+

Vendor ID on

tWRIDON

Venodr ID off

tWRIDOFF

enable delay

tTSEN

a. All parameters assume proper device initialization.

b. Tests for AC timing may be considered at norminal supply voltage levels, but the related specification and device operation are guaranteed for the full

voltage and temperature range specified.

c. CK and CK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFC crossing and VIXCK(AC)

d. Parameter fCKBG4 is required for those devices supporting both 3*tCK and 4*tCK setting for bank groups. Devices supporting only 3*tCK or 4*tCK

need only to specify fCKBG.

e. Parameter fCKPIN applies when the alignment point in MR6, bit A0 is set to “at pins”, the phase difference between the WCK and CK clocks at the

DRAM pins is within tWCK2CKSYNC or tWCK2CK for pin mode and no phase search in WCK2CK training is performed.

f. Parameter fCKRDQS applies when RDQS mode is enabled in AR3, bit A5.

g. Parameter fCKBREFD2 applies when the data input reference voltage in MR7, bit A7 (Half VREFD) is set to VREFD2.

h. Parameter fCKAUTOSYNC applies when WCK2CK Auto Synchronization is enabled in MR7, bit A4.

i. Parameter fCKLF applies when Low Frequency Mode is enabled in MR7, bit A3.

j. By definition the norminal WCK clock cycle time always is 1/2 of the CK clock cycle time (not including jitter).

k. WCK and WCK# single-ended input slew rate must be greater than or equal to 3V/ns. The slew rate is measured between VREFD crossing and

VIXWCK(AC).

Table 44. AC Timings (@1.35V)

H5GQ2H24AFR-R0C 数据表(PDF) 150 Page - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 150 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载