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数据搜索系统，热门电子元器件搜索 |
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STR720 数据表(PDF) 342 Page - STMicroelectronics |
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STR720 数据表(HTML) 342 Page - STMicroelectronics |
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342 / 401 page  STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC) 342/401 ADC Data Register n, n = 0 .. 3 (ADCDATAn) Address Offsets: 00h, 08h, 10h, 18h Reset Values: 0000h Four data registers, one for each of the analogue input channels, are available. The 12 most significant bits will contain the result of the conversion, while the least significant bits of each register should be ignored. Values reported in data registers are expressed in 2’s complement notation. The data registers will be filled in numerical sequence in the round-robin channel mode. In single channel mode, only the selected channel will be updated. Bit 15:0 = DATA[15:0]: DATA sample This read-only register contains the last sampled value on the corresponding channel. 22.4.1 Register map Refer to Table 20 on page 49 for the base address. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[15:0] r Table 71. ADC Register Map Addr. Offset Register Name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 ADCDATA0 DATA[15:0] 08 ADCDATA1 DATA[15:0] 10 ADCDATA2 DATA[15:0] 18 ADCDATA3 DATA[15:0] 20 ADCCSR Reserved OR Res. IE[3:0] Res. AXT A[1:0] DA[3:0] 28 Reserved 30 ADCCPR Reserved PRESC[7:0] |
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