STR720 datasheet(339/401 Pages) STMICROELECTRONICS

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STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC)

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22.3.11 Power Saving Features

The analog circuitry of the ADC block is switched off when bit “ADC_OFF” in the AGCR

power consumption via AVDD / AVSS pins to be minimized (< 1 µA). Due to the fact that the

analog section of ADC is used also to generate reference currents for the proper operation of

clock input pads, it is recommended to disable the ADC by software only after having switched

to a low power mode that is not using clock input pads, as SLOW or STOP mode (see Section

25: POWER REDUCTION MODES on page 364).

The digital section of ADC block can be stopped by using the ordinary clock gating features,

provided on the device.

Note that on power-up, or after switching on “ADC_OFF” bit, the common-mode feedback

circuit can take about 30 oversampling clock cycles to drive the common-mode voltage to its

correct value. For this reason, the first sample should be discarded after activating ADC block.

22.4 Register description

ADC Control/Status Register (ADCCSR)

Address Offset: 20h

Reset Value: 0000h

This register controls the operating mode of the ADC, sets the interrupt enables, contains

status flags for the availability of data and error flags in the event of data being overwritten

before being read.

Bit 15 = Reserved. This bit should be written as ‘0’ and will be read always at ‘0’.

Bit 14 = DEC: DECimation factor

This bit selects the decimation mode between normal mode and low-rate mode, where same

prescaler value can be used to reach very low sampling rates.

0: Normal mode, decimation by 512.

1: Low-rate mode decimation by 5120.

Bit 13 = OR: OverRun

This read-clear bit is used to notify application software that data on one of the channels has

been overwritten before being read.

0: Normal operation. No overrun has occurred.

1: Overrun event occurred. This bit is set by hardware as soon as an overrun condition is

detected and must be cleared by software by explicitly writing it to “0”. Writing “1” into this bit

has no effect.

Res.

DEC

Res

IE[3:0]

Res.

AXT

A[1:0]

DA[3:0]

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