STR720 datasheet(338/401 Pages) STMICROELECTRONICS

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STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC)

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22.3.9

ADC Input Equivalent Circuit

The input equivalent circuit, due to the switching at F

Mod rate of the input capacitance where

the charge taken from the input signal to be measured is stored, can be represented as

follows:

where V

S is the voltage under measurement, RS is the output resistance of the source, VPIN

the voltage the will actually converted and R

IN the input equivalent resistance of the ADC. RIN

is inversely proportional to the modulator oversampling clock and the constant K is equal to

540 [k

Ω][MHz] +/- 20%.

22.3.10 ADC Output Coding

The

Σ−∆ converter produces a digital sample of each analog input channel every 512

oversampling clocks (5120 when low-rate mode is selected). The digital samples in output

from the Sinc3 digital filter are stored in the four ADCDATAn registers as 16-bit samples of

which only the first 12 most significant bits are meaningful. The converted value stored in

ADCDATA[n] is a signed two’s complement value and proportional to the difference (VIN-VCM),

being ideally 0 if the input voltage were VIN = VCM. Since the gain and offset errors previously

described, before actually using the result of the conversion calibration must be performed.

Note

The analog input voltage should not exceed twice the Center Voltage of the

Σ-∆

Modulator (2 * V

CM)

otherwise converter performances cannot be guaranteed.

Remember that the V

CM Voltage has an accuracy of +/- 5% which imposes a

calibration of the converter.

Figure 61. ADC Input Equivalent Circuit

VCM

RIN = K * 1/FMod

VPIN

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