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STR720 数据表(PDF) 341 Page - STMicroelectronics |
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STR720 数据表(HTML) 341 Page - STMicroelectronics |
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341 / 401 page ![]() STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC) 341/401 ADC Clock Prescaler Register (ADCCPR) Address Offset: 30h Reset Value: 0006h Bits 15:7 = Reserved. These bits should be always written as ‘0’. Bits 6:0 = PRESC[6:0]: Prescaler value The 7 bit binary value specified on the clock prescaler register determines the factor by which the ADC input clock will be divided down in order to produce the oversampling clock of the sigma-delta modulator, the actual factor being twice the PRESC register value as illustrated in Table 70 on page 341. The value placed in this register must subsequently generate an oversampling clock frequency not greater than 4 MHz from the master clock applied to the ADC. These bits can only be written by software, any read operation on them returns 0h. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PRESC[6:0] -w Table 70. ADC Prescaler setting Setting Divide Factor 0 Not available (ADC frozen) 1 Not available (ADC frozen) 24 36 48 .. .. 126 252 127 254 |
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