STR720 datasheet(340/401 Pages) STMICROELECTRONICS

340 / 401 page

STR720 - S-D ANALOG/DIGITAL CONVERTER (ADC)

340/401

Bit 12 = Reserved. This bit should be written as ‘0’ and will be read always at ‘0’.

Bits 11:8 = IE[3:0]: Interrupt Enable

This set of bits allows to enable interrupt requests independently for each of the ADC

channels, where bit IE[n] corresponds to ADC channel n.

0: Channel n interrupt disabled.

1: Channel n interrupt enabled.

Bit 7 = Reserved. This bit should be written as ‘0’ and will be read always at ‘0’.

Bit 6 = AXT: Addressing eXTernal enable

This bit allows to enable the single-channel operation, configuring the ADC to convert

repeatedly the channel identified by A[1:0] bits of this register.

0: Round-robin addressing enabled.

1: Single-channel addressing enabled.

Bits 5:4 = A[1:0]: channel Address

These bits select the external channel to be sampled when external addressing is enabled.

Bits 3:0 = DA[3:0]: Data Available

This read-clear set of bits allows to determine on which channel data register a new sample is

ready to be read, where bit DA[n] corresponds to ADC channel n. They are set by hardware as

soon as a new sample on the corresponding channel is available and they can be cleared

explicitly by writing them to “0” or indirectly when the corresponding data register is read.

Writing “1” into these bits has no effect.

0: No sample is available on the corresponding channel.

1: New sample available on the corresponding channel.

These bits also act as interrupt flags for the corresponding channels.

STR720 数据表(PDF) 340 Page - STMicroelectronics