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H5GQ2H24AFR-R0C 数据表(PDF) 130 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 130 Page - Hynix Semiconductor |
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130 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 130 H5GQ2H24AFR Notes: 1. This provides a minimum of 0.9V to a maximum of 1.2V, and is nominally 70% of VDDQ with POD15. If POD135, this provides a minimum of 0.845V to a maximum of 1.045V, and is nominally 70% of VDDQ. DRAM timings relative to CK cannot be guaranteed if these limits are exceeded. 2. For AC operations, all DC clock requirements must be satisfied as well. 3. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same. 4. VIDCK is the magnitude of the difference between the input level in CK and the input level on CK#. The input reference level for signals other than CK and CK# is VREFC. 5. VIDWCK is the magnitude of the difference between the input level in WCK and the input level on WCK#. The input reference level for signals other than WCK and WCK# is either VREFD, VREFD2 or the internal VREFD. 6. The CK and CK# input reference level (for timing referenced to CK and CK#) is the point at which CK and CK# cross. Please refer to the applicable timings in the AC timings table (Table 44). 7. The WCK and WCK# input reference level (for timing referenced to WCK and WCK#) is the point at which WCK and WCK# cross. Please refer to the applicable timings in the AC Timings table (Table 44). 8. VREFD is either VREFD, VREFD2 or the internal VREFD. 9. The slew rate is measured between VREFC crossing and VIXCK(AC). 10. The slew rate is measured between VREFD crossing and VIXWCK(AC). 11. Figure illustrates the exact relationship between (CK‐CK#) or (WCK‐WCK#) and VID(AC), VID(DC) and tDVAC 12. Ringback below VID(DC) is not allowed. 13. tDVAC is not measured in and of itself as a compliance specification, but is relied upon in measurement of clock operating conditions and clock related parameters. Table 41. Clock Input Operating Conditions POD15 POD135 Parameter Symbol Min Max Min Max Unit Note Clock Input Mid‐Point Voltage; CK and CK# VMP (DC) VREFC ‐ 0.10 VREFC + 0.10 VREFC ‐ 0.10 VREFC + 0.10 V1, 6 Clock Input Differential Voltage; CK and CK# VIDCK (DC) 0.22 0.198 V 4, 6 Clock Input Differential Voltage; CK and CK# VIDCK (AC) 0.40 0.36 V 2, 4, 6 Clock Input Differential Voltage; WCK and WCK# VIDWCK (DC) 0.20 0.18 V 5, 7 Clock Input Differential Voltage; WCK and WCK# VIDWCK (AC) 0.30 0.27 2, 5, 7 Clock Input Voltage Level; CK, CK#, WCK and WCK# single ended VIN ‐0.30 VDDQ + 0.30 ‐0.30 VDDQ + 0.30 CK/CK# Single ended slew rate CKslew 3 2.7 V/ns 9 WCK/WCK# Single ended slew rate WCKslew 3 2.7 V/ns 10 Clock Input Crossing Point Voltage; CK and CK# VIXCK (AC) VREFC ‐ 0.12 VREFC + 0.12 VREFC ‐ 0.108 VREFC + 0.108 V2, 3, 6 Clock Input Crossing Point Voltage; WCK and WCK# VIXWCK (AC) VREFD ‐ 0.10 VREFD + 0.10 VREFD ‐ 0.09 VREFD + 0.09 V 2, 3, 7, 8 Allowed time before ringback of CK/ WCK below VIDCK/WCK(AC) tDVAC ps 11, 12, 13 |
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