H5GQ2H24AFR-R0C datasheet(107/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

107

H5GQ2H24AFR

5.14. AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function as described

above, but without requiring an explicit command. This is accomplished by using A8 (A8 = High), to

enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank

/ row that is addressed with the READ or WRITE command is automatically performed upon completion

of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each

individual READ or WRITE command.

Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user

must not issue another command to the same bank until the precharge time (tRP) is completed. This is

determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described

for each burst type in the OPERATION section of this specification.

5.15. REFRESH

The REFRESH command is used during normal operation of the GDDR5 SGRAM. The command is non

persistent, so it must be issued each time a refresh is required. A minimum time tRFC is required between

two REFRESH commands. The same rule applies to any access command after the refresh operation. All

banks must be precharged prior to the REFRESH command.

The refresh addressing is generated by the internal refresh controller. This makes the address bits ʺDonʹt

Careʺ during a REFRESH command. The GDDR5 SGRAM requires REFRESH cycles at an average peri‐

odic interval of tREFI(max). The values of tREFI for different densities are listed in Table 6. To allow for

improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight REFRESH commands can be posted to the GDDR5 SGRAM, and

the maximum absolute interval between any REFRESH command and the next REFRESH command is 9 *

tREFI.

During REFRESH, and when bit A2 in MR5 is set to 0, WRTR, RDTR, and LDFF commands are allowed at

time tREFTR after the REFRESH command, which enable (incremental) data training to occur in parallel

with the internal refresh operation and thus without loss of performance on the interface. See READ Train‐

ing and WRITE Training for details.

As impedance updates from the auto‐calibration engine may occur with any REFRESH command, it is safe

to only issue NOP commands during tKO period to prevent false command, address or data latching

resulting from impedance updates.

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