H5GQ2H24AFR-R0C datasheet(109/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

109

H5GQ2H24AFR

5.16. SELF‐REFRESH

Self‐Refresh can be used to retain data in the GDDR5 SGRAM, even if the rest of the system is powered

down. When in the Self‐Refresh mode, the GDDR5 SGRAM retains data without external clocking. The

SELF REFRESH ENTRY command (see Figure 73) is initiated like a REFRESH command except that CKE#

is pulled HIGH. SELF REFRESH ENTRY is only allowed when all banks are precharged with tRP satisfied,

and when the last data element or CRC data element from a preceding READ or WRITE command have

been pushed out (tRDSRE). NOP commands are required until tCKSRE is met after the entering Self‐Refresh.

The PLL is automatically disabled upon entering Self‐Refresh and is automatically enabled and reset upon

exiting Self‐Refresh. If the GDDR5 SGRAM enters Self‐Refresh with the PLL disabled, it will exit Self‐

Refresh with the PLL disabled.

Once the SELF REFRESH ENTRY command is registered, CKE# must be held HIGH to keep the device in

Self‐Refresh mode. When the device has entered the Self‐Refresh mode, all external control signals, except

CKE# and RESET# are “Don’t care”. For proper Self‐Refresh operation, all power supply and reference

pins (VDD, VDDQ, VSS, VSSQ, VREFC, VREFD) must be at valid levels. The GDDR5 SGRAM initiates a

minimum of one internal refresh within tCKE period once it enters Self‐Refresh mode. The address, com‐

mand, data and WCK pins are in ODT state, and the EDC pins drive a HIGH.

The clock is internally disabled during Self‐Refresh operation to save power. The minimum time that the

GDDR5 SGRAM must remain in Self‐Refresh mode is tCKE. The user may change the external clock fre‐

quency or halt the external CK and WCK clocks tCKSRE after Self‐Refresh entry is registered. However, the

clocks must be restarted and stable tCKSRX before the device can exit Self‐Refresh operation.

The procedure for exiting Self‐Refresh requires a sequence of events. First, the CK and WCK clocks must

be stable prior to CKE# going back LOW. A delay of at least tXSNRW must be satisfied before a valid com‐

mand not requiring a locked PLL can be issued to the device to allow for completion of any internal

refresh in progress. Before a command requiring a locked PLL can be applied, a delay of at least tXSRW

must be satisfied.

During Self‐Refresh the on‐die termination (ODT) and driver will not be auto‐calibrated. Therefore, it is

recommended that the ODT and driver be recalibrated by the controller upon exiting Self‐Refresh. Alter‐

natively, if changes in voltage and temperature are tracked or known to be bounded then the provided

Voltage and Temperature Variation tables may be consulted to determine if recalibration is necessary.

Upon exit from Self‐Refresh, the GDDR5 SGRAM can be put back into Self‐Refresh mode after waiting at

least tXSNRW period and issuing one extra REFRESH command.

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