H5GQ2H24AFR-R0C datasheet(112/172 Pages) HYNIX

112 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

112

H5GQ2H24AFR

5.17. POWER‐DOWN

GDDR5 SGRAMs requires CKE# to be LOW at all times an access is in progress: from the issuing of a

READ or WRITE command until completion of the burst. For READs, a burst completion is defined as

when the last data element including CRC has been transmitted on the DQ outputs, for WRITEs, a burst

completion is defined as when the last data element has been written to the memory array and CRC data

has been returned to the controller.

POWER‐DOWN is entered when CKE# is registered HIGH. If POWER‐DOWN occurs when all banks are

idle, this mode is referred to as precharge POWER‐DOWN; if POWER‐DOWN occurs when there is a row

active in any bank, this mode is referred to as active POWER‐DOWN. Entering POWER‐DOWN deacti‐

vates the input and output buffers, excluding CK, CK#, WCK, WCK#, RESET#, EDC pins and CKE#. The

input buffers for WCK and WCK# can be turned off if the LP2 bit in MR5 is on.

For maximum power savings, the user has the option of disabling the PLL prior to entering POWER‐

DOWN. In that case, on exiting POWER‐DOWN, WCK2CK training is required to set the internal synchro‐

nizers which will include the enabling of the PLL, PLL reset, and tLK clock cycles must occur before any

READ or WRITE command can be issued.

While in power‐down, CKE# HIGH and stable CK and WCK signals must be maintained at the device

inputs. The EDC pins continuously drive the EDC hold pattern; if the controller does not require CDR,

users may program the EDC hold pattern to ’1111’ prior to entering power‐down mode. POWER‐DOWN

duration is limited by the refresh requirements of the device.

The POWER‐DOWN state is synchronously exited when CKE# is registered LOW (in conjunction with a

NOP or DESELECT command). A valid executable command may be applied tXPN cycles later. The min.

power‐down duration is specified by tPD.

Figure 75. Power-Down Entry and Exit

Note:

CK#

CMD

PDE

NOP

Tb0

Ta1

Ta2

PDX

Valid

NOP

tCPDED

CKE#

NOP

tPD

Enter Power‐Down Mode

Exit Power‐Down Mode

tXPN

tRDSRE or tWRSRE

WCK

WCK#

NOP

Ta0

Donʹt Care

H5GQ2H24AFR-R0C 数据表(PDF) 112 Page - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 112 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载