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H5GQ2H24AFR-R0C 数据表(PDF) 114 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 114 Page - Hynix Semiconductor |
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114 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 114 H5GQ2H24AFR Notes 1. This table applies when CKE#n‐1 was LOW and CKE#n is LOW (see <Link>Table 29) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank‐specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled. Write: A WRITE burst has been initiated, with auto precharge disabled. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and <Link>Table 30, and according to <Link>Table 31. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the “row active” state. Read w/Auto‐Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto‐Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of a REFRESH command and ends when tRC is met. Once tRC is met, the GDDR5 SGRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the GDDR5 SGRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. READ or WRITE: Starts with the registration of the ACTIVE command and ends the last valid data nibble. 6. All states and sequences not shown are illegal or reserved. 7. Not bank‐specific; requires that all banks are idle, and bursts are not in progress. 8. May or may not be bank‐specific; if multiple banks are to be precharged, each must be in a valid state for precharging. Table 30 Truth Table – Current State Bank n – Command To Bank n CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES Any H X X X DESELECT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) Idle L L H H ACTIVE (select and activate row) L L L H REFRESH 4 L L L L MODE REGISTER SET 4 Row Active L H L H READ (select column and start READ burst) 6 L H L L WRITE (select column and start WRITE burst) (WOM, WSM or WDM) 6 L L H L PRECHARGE (deactivate row in bank or banks) 5 Read (Auto Precharge Disabled) L H L H READ (select column and start new READ burst) 6 L H L L WRITE (select column and start WRITE burst) (WOM, WSM or WDM) 6, 8 L L H L PRECHARGE (only after the READ burst is complete 5 Write (Auto Precharge Disabled) (WOM, WSM or WDM) L H L H READ (select column and start READ burst) 6, 7 L H L L WRITE (select column and start new WRITE burst) (WOM, WSM or WDM) 6 L L H L PRECHARGE (only after the WRITE burst is complete) 5, 7 |
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