H5GQ2H24AFR-R0C datasheet(118/172 Pages) HYNIX

118 / 172 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

118

H5GQ2H24AFR

The WCK2CK training should be performed prior to entering RDQS mode. No WCK2CK training can be

done when the RDQS mode is active. 

Figure 76. RDQS Mode Timings

EDC1 and EDC3 can be treated as pseudo‐differential to EDC0 and EDC2 respectively, by setting the

EDC13Inv field, bit A11 in MR4, as shown in Table 34.

Table 33 EDC pin behavior in RDQS mode including pseudo‐differential RDQS

MRS Set

READ/RDTR

NOP

(except

RD/RDTR/

PDN/SRF)

POWER‐

DOWN/SELF

REFRESH

RDQS Mode

WCK2CK

Training

EDC13 Invert

EDC02

Output

EDC13

Output

EDC0123

Output

EDC0123

Output

Off

RDQS

1111

High

RDQS

Inverted

RDQS

1111

High

CK#

CMD

NOP

MRS

1. MRA = Mode Register address and opcode; BA = bank address; CA = column address

READ

ADDR

MRA MRA

NOP

MRS

NOP

WCK

WCK#

EDC

CLmrs

BA CA

MRA MRA

tMRD

EDC

Hold

NOP

tMRD

EDC

Hold

Enter RDQS Mode

Exit RDQS Mode

Ta0

Ta1

Tb0

Tb1

Tb2

Tb3

Tb4

Tb5

Tc0

Donʹt Care

3. Before the READ command, an ACTIVE (ACT) command is required to be issued to the GDDR5 SGRAM and tRCDRD must be met.

4. tWCK2DQO = 0 is shown for illustration purposes.

2. WCK and CK are shown aligned (tWCK2CKPIN=0, tWCK2CK=0) for illustration purposes. WCK2CK training determines the needed offset between WCK and CK.

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