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H5GQ2H24AFR-R0C 数据表(PDF) 121 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 121 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
121
H5GQ2H24AFR
Figure 77. DVS Sequence
CK#
CK
CMD
SRE
NOP
T0
T1
T2
Ta0
Tb2
Tb0
Tb1
Td0
SRX
PREA
Valid
NOP
tCPDED
CKE#
NOP
tCKSRE
tCKSRX
tRP
Tc0
Enter Self‐Refresh Mode 
Exit Self‐ Refresh Mode
tXSNRW
tXSRW
tRDSRE or tWRSRE
Self refresh exit requires WCK2CK training prior to any WRITE or READ operation
At least one REFRESH command shall be issued after tXSNRW for output driver and termination impedance updates  
NOP
Donʹt Care
Voltage ramp
tVS
VDD,
VDDQ
Voriginal
Vnew
VSS, VSSQ
Voriginal > Vnew shown as an example of a voltage change
Note) PREA (Precharge All) command shall be issued after SRX (Self Refresh).



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