H5GQ2H24AFR-R0C datasheet(123/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

123

H5GQ2H24AFR

5.23. DUTY CYCLE CORRECTOR (DCC)

As GDDR5 SGRAMs can operate with the PLL/DLL off during normal operation, the use of a Duty Cycle

Corrector (DCC) can correct for the duty cycle error of the WCK clocks, resulting in improved timing mar‐

gins for Reads and Writes. The DCC can be enabled at any time; however it is recommended to enable the

DCC prior to WCK2CK training because any shift of rising and falling WCK edges can impact the

WCK2CK training results.

DCC operation is controlled by MR7 bits A11 and A10. Initially a “DCC reset” command will reset the

internal correcting code. After tMRD a “DCC start” command may be given which starts the actual duty

cycle correction. The DCC must be held in this state for a minimum duration of tDCC. After tDCC is met, a

DCC hold can be set to terminate the duty cycle correction and hold the DCC code or the DCC can be left

on to dynamically correct the duty cycle. Disabling the DCC requires a series of two MRS command: at

first, a “DCC reset” resets the internal correcting code, then a “DCC off” will fully disable the DCC. The

DCC may also be fully disabled in the “DCC reset” state, depending on design implementation.

DCC can correct the duty cycle error within the range of ±100ps.

Figure 78. Timing Diagram of DCC Control Signals

Table 35 DCC Timings

Parameter

Symbol

Min

Max

Unit

Required time for duty cycle corrector

tDCC

1300

‐

tCK

Training

PLL Reset

DCC start

DCC hold or not

Enter WCK2CK

Training (reset WCK

divide by circuits)

Enter WCK2CK

Training (sets data

synchronizers, resets

FIFO pointers)

WCK#

WCK

CK#

CMD

NOP

MRS

NOP

MRS

NOP

MRS

A.C.

tWCK2MRS

tMRD

tWCK2TR

tDCC

tLK

tMRD

Start WCK2CK Phase

DCC reset

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