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H5GQ2H24AFR-R0C 数据表(PDF) 124 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 124 Page - Hynix Semiconductor |
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124 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 124 H5GQ2H24AFR DCC control signals •DCC reset : Initializes the DCC code and shall be issued when WCK is stable •DCC start :Enables the DCC to update the DCC code •DCC hold/off : Stops the DCC from undating and holds the DCC code DCC sequence •Step 1) Enable DCC reset(MRS7 A11:1. A10:0) before entering WCK2CK training •Step 2) Enalble DCC start(MRS7 A11:0, A10:1) after WCK&WCKB are stabilized during tWCK2TR •Step 3) Wait tDCC(>1300cycles) for DCC operation •Step 4) Enale DCC hold(MRS7 A11:0, A10:0) before starting WCK2CK Phase Training •Step 5) If continual DCC update is required, enable DCC start (MRS7 A11:0, A10:1) after EXIT WCK Training Table 36 DCC Control Signals A11 A10 DCC 00 no DCC & DCC off or hold 01 DCC start 10 DCC reset 11 RFU |
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