H5GQ2H24AFR-R0C datasheet(120/172 Pages) HYNIX

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.2 /Nov. 2011

120

H5GQ2H24AFR

5.21. DYNAMIC VOLTAGE SWITCHING (DVS)

GDDR5 SGRAM’s allow the supply voltage to be changed during the course of normal operation using the

GDDR5 Dynamic Voltage Switching (DVS) feature. By using DVS the GDDR5 SGRAM’s power consump‐

tion can be reduced whenever only a fraction of the maximum available bandwidth is required by the cur‐

rent work load.

DVS requires the GDDR5 SGRAM to be properly placed into self refresh before the voltage is changed

from the exising stable voltage, Voriginal to the new desired voltage Vnew . The DVS procedure may also

require changes to the VDD Range mode register using MR7 bits A8 and A9, depending on whether the

feature is supported. The datasheet shall be consulted regarding the supported supply voltages for DVS,

and any dependencies of AC timing parameters on the selected supply voltage.

Clock frequency changes can also take place before or after entering self refresh mode using the standard

Clock Frequency Change procedure. A clock frequency change in conjunction with DVS is required if tCK

is less than tCKmin supported by Vnew . In this case normal device operation including self refresh exit is

not guaranteed without a frequency change. Changing the frequency while in self refresh is the most safe

procedure.

Once self refresh is entered, tCKSRE must be met before the supply voltage is allowed to transition from

Voriginal to Vnew. After VDD and VDDQ are stable at Vnew, tVS must be met to allow for internal voltages

in the GDDR5 SGRAM to stabilize before self refresh mode may be exited. During the voltage transition

the voltage must not go below Vmin of the lower voltage of either Voriginal or Vnew in order to prevent false

chip reset. Vmin is the minimum voltage allowed by VDD or VDDQ in the DC operating conditions table.

VREF shall continue to track VDDQ.

DVS Procedure

Step 1) Complete all operations and precharge all banks.

Step 2) Issue an MRS command to set VDD Range to proper values for Vnew. This step is only required when the VDD

Range mode register field is supported by the GDDR5 SGRAM.

Step 3) Enter self refresh mode. Self refresh entry procedure must be met.

Step 4) Wait required time tCKSRE before changing voltage to Vnew.

Step 5) Change VDD and VDDQ to Vnew.

Step 6) Wait required time tVS for voltage stabilization.

Step 7) Exit self refresh. The self refresh exit procedure must be met.

Step 8) Issue MRS commands to adjust mode register settings as desired (e.g. latencies, PLL on/off, CRC on/off, RDQS

mode on/off).

Step 9) Perform any interface training as required.

Step 10) Continue normal operation.

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