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H5GQ2H24AFR-R0C 数据表(PDF) 116 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 116 Page - Hynix Semiconductor |
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116 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 116 H5GQ2H24AFR 4a. The read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, ACTIVE, PRECHARGE, READ and WRITE commands to the other bank may be applied. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). 4b. The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. 5. REFRESH and MODE REGISTER SET commands may only be issued when all banks are idle. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. *** CLmrs = CAS latency (CL) BL = Burst length WLmrs = WRITE latency tWTR = tWTRL if Bank Groups enabled and access to the same bank group, otherwise tWTR=tWTRS tCCD = tCCDL if Bank Groups enabled and access to the same bank group, otherwise tCCD=tCCDS Table 32 Minimum Delay Between Commands to Different Banks with Auto Precharge Enabled From Command To Command Minimum delay (with concurrent auto precharge) WRITE with AUTO PRECHARGE (WOMA) READ or READ with AUTO PRECHARGE [WLmrs + (BL/4)] tCK + tWTR *** WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 2 * tCK PRECHARGE 1* tCK ACTIVE 1* tCK WRITE with AUTO PRECHARGE (WDMA) READ or READ with AUTO PRECHARGE [WLmrs+ (BL/4)] tCK + tWTR *** WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 2 * tCK PRECHARGE 2* tCK ACTIVE 2* tCK WRITE with AUTO PRECHARGE (WSMA) READ or READ with AUTO PRECHARGE [WLmrs + (BL/4)] tCK + tWTR *** WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/WDMA) 3 * tCK (JEDEC : MAX[tccd, 3 * tCK ] PRECHARGE 3* tCK ACTIVE 3* tCK READ with AUTO PRECHARGE READ or READ with AUTO PRECHARGE 2 * tCK WRITE or WRITE with AUTO PRECHARGE (WOM/WOMA, WSM/WSMA or WDM/ WDMA) [CLmrs + (BL/4) + 2 (JEDEC: tccd) ‐ WLmrs] * tCK *** PRECHARGE 1* tCK ACTIVE 1* tCK |
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