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H5GQ2H24AFR-R0C 数据表(PDF) 158 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 158 Page - Hynix Semiconductor |
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158 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 158 H5GQ2H24AFR 7.1. SIGNALS Table 54. Ball-out Description SYMBOL TYPE DESCRIPTION CK, CK# Input Clock: CK and CK# are differential clock inputs. Command inputs are latched on the rising edge of CK. Address inputs are latched on the rising edge of CK and the rising edge of CK#. All latencies are referenced to CK. CK and CK# are externally terminated. WCK01, WCK01#, WCK23, WCK23# Input Write Clocks: WCK and WCK# are differential clocks used for WRITE data capture and READ data output. WCK01/WCK01# is associated with DQ0‐DQ15, DBI0#, DBI1#, EDC0 and EDC1. WCK23/WCK23# is associated with DQ16‐DQ31, DBI2#, DBI3#, EDC2 and EDC3. CKE# Input Clock Enable: CKE# LOW activates and CKE# HIGH deactivates the internal clock, device input buffers, and output drivers. Taking CKE# HIGH provides PRECHARGE POWER‐ DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER‐DOWN (row ACTIVE in any bank). CKE# must be maintained LOW throughout read and write accesses. The value of CKE# latched at power‐up with RESET# going High determines the termination value of the address and command inputs. CS# Input Chip Select: CS# LOW enables and CS# HIGH disables the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. RAS#, CAS#,WE# Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. BA0–BA3 Input Bank Address Inputs: BA0 ‐ BA3 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0‐BA3 also determine which Mode Register is accessed with an MODE REGISTER SET command. BA0‐BA3 are sampled with the rising edge of CK. A0–A12 Input Address Inputs: A0‐A12 provide the row address for ACTIVE commands, A0‐A5 (A6) provide the column address and A8 defines the auto precharge function for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0 ‐BA3) or all banks (A8 HIGH). The address inputs also provide the op‐code during a MODE REGISTER SET command and the data bits during a LDFF command. A8‐A11(A12) are sampled with the rising edge of CK and A0‐A7 are sampled with the rising edge of CK#. DQ0–31 I/O Data Input/Output: 32‐bit data bus DBI#0‐3 I/O Data Bus Inversion. DBI#0 is associated with DQ0‐DQ7, DBI#1 is associated with DQ8‐DQ15, DBI#2 is associated with DQ16‐DQ23, DBI#3 is associated with DQ24‐DQ31. EDC0‐3 Output Error Detection Code. The calculated CRC data is transmitted on these pins. In addition these pins drive a ‘hold’ pattern when idle and can be used as an RDQS function. EDC0 is associated with DQ0‐DQ7, EDC1 is associated with DQ8‐DQ15, EDC2 is associated with DQ16‐DQ23, EDC3 is associated with DQ24‐DQ31. ABI# Input Address Bus Inversion VddQ Supply I/O Power Supply. Isolated on the die for improved noise immunity. VssQ Supply I/O Ground: Isolated on the die for improved noise immunity. Vdd Supply Power Supply Vss Supply Ground Vrefd Supply Reference Voltage for DQ, DBI#, and EDC pins. Vrefc Supply Reference Voltage for address and command pins. Vpp Supply Pump Voltage MF Reference Mirror Function: VDDQ CMOS input. Must be tied to power or ground. ZQ Reference External Reference Pin for autocalibration |
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