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H5GQ2H24AFR-R0C 数据表(PDF) 159 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 159 Page - Hynix Semiconductor |
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159 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 159 H5GQ2H24AFR Figure 82 clarifies the use of the MF=0 and MF=1 ball‐outs in x16 mode and why the bytes are renumbered to give the controller the view of the same bytes that a controller sees with a single x32 device. This is important for Address Training, DM and EDC functionality. For more details see the x16 enable and MF enable section. RFU Reserved for Future Use NC Not connected SEN Input Scan enable. VDDQ CMOS input. Must be tied to the ground when not in use. RESET# Input Reset Pin. VDDQ CMOS input. RESET# Low asynchronously initiates a full chip reset. With RESET# Low all ODTs are disabled.A full chip reset may be performed at any time by pulling RESET# Low. Table 54. Ball-out Description SYMBOL TYPE DESCRIPTION |
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