数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

H5GQ2H24AFR-R0C 数据表(PDF) 161 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 161 Page - Hynix Semiconductor

Back Button H5GQ2H24AFR-R0C Datasheet HTML 157Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 158Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 159Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 160Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 161Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 162Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 163Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 164Page - Hynix Semiconductor H5GQ2H24AFR-R0C Datasheet HTML 165Page - Hynix Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 161 / 172 page
background image
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
161
H5GQ2H24AFR
 7.2. ON DIE TERMINATION (ODT)
GDDR5 SGRAMs support multiple termination modes for its high speed input signals. When the termina‐
tion is enabled for a receiver, an impedance defined for that termination mode is applied between that 
input receiver and the VDDQ supply rail. This is commonly referred to as VDDQ termination. Registers 
have been defined to control the termination modes. ADD/CMD Termination is controlled using MR1 bits 
A4 and A5. Data termination is controlled using MR1 bits A2 and A3. WCK termination is controlled 
using MR3 bits A8 and A9.
Table 55 includes all the high speed GDDR5 SGRAM signals whose receivers include on die termination to 
VDDQ and whether their termination can be disabled by ADD/CMD Term, DQ Term, or WCK Term. A 
“Yes” indicates whether the mode register field controls termination for the signal. 
Table 55. Signals Affected by Termination Control Registers
      ADD/CMD Term
 MR1 (A4,A5)
    DQ Term
 MR1 (A2,A3)
    WCK Term 
MR3 (A8,A9)
Signal
x32 
x16
x32 
x16 
x32 
x16 
RAS#, CAS#, WE, CS#, CKE#
Yes
Yes
No
No
No
No
A10/A0, A9/A1, BA0/A2, BA3/A3,
BA2/A4, BA1/A5, A11/A6, A8/A7, 
A12/RFU/(NC), ABI#
Yes
Yes
No
No
No
No
DQ[7:0], DBI0#
No
No
Yes
Yes
No
No
DQ[15:8], DBI1#
No
Disabled
Yes
Disabled
No
Disabled
DQ[23:16], DBI2#
No
No
Yes
Yes
No
No
DQ[31:24], DBI3#
No
Disabled
Yes
Disabled
No
Disabled
WCK01, WCK01#, WCK23, WCK23#
No
No
No
No
Yes
Yes



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com