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H5GQ2H24AFR-R0C 数据表(PDF) 165 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 165 Page - Hynix Semiconductor |
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165 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 165 H5GQ2H24AFR Figure 85. System view for x32 mode vs. x16 mode Figure 85 and Figure 86 show examples of the board channels and topologies that are supported in GDDR5 in order to illustrate the expected usage of x16 mode and the MF pin. Table 57. x16 mode and MF MODE MF EDC1 (MF=0) or EDC2 (MF=1) x16 non‐mirrored VSSQ VSSQ x32 non‐mirrored VSSQ VDDQ (terminated by the system or controller) x16 mirrored VDDQ VSSQ x32 mirrored VDDQ VDDQ (terminated by the system or controller) Byte1 Byte3 Byte2 Byte0 ADD/ CMD ADD/ CMD Byte1 Byte3 Byte2 Byte0 DQ0‐DQ7,DBI0# EDC0 DQ8‐DQ15,DBI1# EDC1 DQ16‐DQ23,DBI2# EDC2 DQ24‐DQ31,DBI3# EDC3 WCK01,WCK01# WCK23,WCK23# Address Bus Command Bus CK,CK# GDDR5 x32 CK,CK# EDC2 EDC1 RESET RESET# MF MF VDDQ VSSQ MF VSSQ GDDR5 x16 GDDR5 x16 Address Bus Command Bus DQ0‐DQ7,DBI0# EDC0 DQ8‐DQ15,DBI1# EDC1 DQ16‐DQ23,DBI2# EDC2 DQ24‐DQ31,DBI3# EDC3 WCK01,WCK01# WCK23,WCK23# |
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