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H5GQ2H24AFR-R0C 数据表(PDF) 169 Page - Hynix Semiconductor |
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H5GQ2H24AFR-R0C 数据表(HTML) 169 Page - Hynix Semiconductor |
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169 / 172 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.2 /Nov. 2011 169 H5GQ2H24AFR Notes: 1. When SEN is asserted, no commands are to be executed by the GDDR5 SGRAM. This applies to both user commands and manufacturing commands which may exist while RESET# is deasserted. 2. All scan functionality is valid only after the appropriate power‐up (Steps 1‐4 of initialization sequence). 3. In scan mode, all ODT will be disabled. Table 59. Scan Pin Description PACKAGE BALL SYMBOL NORMAL FUNCTION TYPE DESCRIPTION J‐2SSH RESET# Input Scan Shift: capture the data input from the pad at logic LOW and shift the data on the chain at logic HIGH. G‐12 SCK CS# Input Scan Clock. Not a true clock, could be a single pulse or series of pulses. All scan inputs will be referenced to the rising edge of the scan clock. C‐2SOUT EDC0 Output Scan Output. J‐10 SEN RFU Input Scan Enable: logic HIGH enables scan mode. Scan mode is disabled at logic LOW. Must be tied to VSSQ when not in use. J‐1SOE# MF Input Scan Output Enable: enables (registered LOW) and disables (registered HIGH) SOUT data. This pin will be tied to VDDQ or GND through a resistor (typically 1K Ohm) for normal operation. Tester needs to overdrive this pin to guarantee the required input logic level in scan mode. Table 60. Scan AC Electrical Characteristics PARAMETER/CONDITION SYMBOL MIN MAX UNIT S NOTES Clock Clock cycle time tSCK 40 ‐ ns 1 Scan Command Time Scan enable setup time tSES 20 ‐ ns 1 Scan enable hold time tSEH 20 ‐ ns 1 Scan command setup time for SSH, SOE# and SOUT tSCS 14 ‐ ns 1 Scan command hold time for SSH, SOE# and SOUT tSCH 14 ‐ ns 1 Scan Capture Time Scan capture setup time tSDS 10 ‐ ns 1 Scan capture hold time tSDH 10 ‐ ns 1 Scan Shift Time |
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