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H5GQ2H24AFR-R0C 数据表(PDF) 172 Page - Hynix Semiconductor

部件名 H5GQ2H24AFR-R0C
功能描述  2Gb (64Mx32) GDDR5 SGRAM
PDF  172 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5GQ2H24AFR-R0C 数据表(HTML) 172 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.2 /Nov. 2011
172
H5GQ2H24AFR
Figure. 92 Internal Block Diagram
DQ2
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
DQ1
DQ3
WCK01#
SSH, Scan Shift Pin RESET#   
SCK, Scan Clock Pin CS# 
SOUT, Scan Out Pin EDC0
SEN, Scan Enable Pin SEN 
SOE#, Scan Output Enable Pin MF   
Pins under test
Dedicated Scan D FF per signal under test
Signals in scan chain:
DQ[31:0], EDC[3:1], DBI#[3:0], 
WCK01, WCK01#, WCK23, WCK23#,
RAS#, CAS#, WE#, CKE#, ABI#, 
A[7:0]***, CK, CK#, ZQ
Note: A[7:0]*** are multiplexed pins and 
represent A[12:8] and BA[3:0]
Signals not in the scan chain:
VDDQ, VSSQ, VDD, VSS, VREFx



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