CS5530 datasheet(25/241 Pages) NSC

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Signal Definitions (Continued)

GNT#

D24

5VT

PCI Bus Grant

GNT# is asserted by an arbiter that indicates to the CS5530 that access

to the PCI bus has been granted.

GNT# should connect to GNT0# of the GXLV processor and function as

the highest-priority PCI master.

HOLD_REQ#

H26

Strap

Option

PCI Bus Hold Request

This pin’s function as HOLD_REQ# is no longer applicable.

5VT

StrapOptionSelect Pin

Pin H26 is a strap option select pin. It allows selection of which address

bits areusedasthe IDSEL.

Strap pin H26 low: IDSEL = AD28 (Chipset Register Space) and AD29

(USB Register Space)

Strap pin H26 high: IDSEL = AD26 (Chipset Register Space) and AD27

(USB Register Space)

FRAME#

C23

I/O

t/s

5VT

PCI Cycle Frame

FRAME# is asserted to indicate the start and duration of a transaction. It

is deasserted on the final data phase.

FRAME# is an input when the CS5530 is a PCI slave.

IRDY#

B24

I/O

t/s

5VT

PCI Initiator Ready

IRDY# is driven by the master to indicate valid data on a write transaction,

or that it is ready to receive data on a read transaction.

When the CS5530 is a PCI slave, IRDY# is an input that can delay the

beginning of a write transaction or the completion of a read transaction.

Wait cycles are inserted until both IRDY# and TRDY# are asserted

together.

TRDY#

B23

I/O

t/s

5VT

PCI Target Ready

TRDY# is asserted by a PCI slave to indicate it is ready to complete the

current data transfer.

TRDY# is an input that indicates a PCI slave has driven valid data on a

read or a PCI slave is ready to accept data from the CS5530 on a write.

TRDY# is an output that indicates the CS5530 has placed valid data on

AD[31:0] during a read or is ready to accept the data from a PCI master

on a write.

Wait cycles are inserted until both IRDY# and TRDY# are asserted

together.

STOP#

E26

I/O

t/s

5VT

PCI Stop

As an input, STOP# indicates that a PCI slave wants to terminate the cur-

rent transfer. The transfer will either be aborted or retried. STOP# is also

used to end a burst.

As an output, STOP# is asserted with TRDY# to indicate a target discon-

nect, or without TRDY# to indicate a target retry. The CS5530 will assert

STOP# during any cache line crossings if in single transfer DMA mode or

if busy.

2.2.4

PCI Interface (Continued)

Signal Name

No.

Type

Description

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