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Functional Description (Continued)

3.2

PCI BUS INTERFACE

The PCI bus interface is compliant with the PCI Bus Spec-

ification Rev. 2.1.

The CS5530 acts as a PCI target for PCI cycles initiated

by the processor or other PCI master devices, or as an ini-

tiator for DMA, ISA, IDE, and audio master transfer cycles.

It supports positive decode for memory and I/O regions

and is the subtractive decode agent on the PCI bus. The

CS5530 also generates address and data parity and per-

forms parity checking. A PCI bus arbiter is not part of the

CS5530; however, one is included in the GXLV processor.

The PCI Command Register, located at F0 Index 04h

(Table 3-2), provides the basic control over the CS5530’s

ability to respond and perform PCI bus accesses.

3.2.1

PCI Initiator

The CS5530 acts as a PCI bus master on behalf of the

DMA controller or ISA, IDE, and audio interfaces. The

REQ# and GNT# signals are used to arbitrate for the PCI

bus.

Note:

In a GXLV processor-based system, the

REQ#/GNT# signals of the CS5530 should con-

nect to the REQ0#/GNT0# of the processor. This

configuration ensures that the CS5530 is treated

as a non-preemptable PCI master by the proces-

sor.

TheCS5530asserts REQ# in response toabus master-

ing or DMA request for ownership of the PCI bus. GNT# is

asserted by the PCI arbiter (i.e., processor) to indicate

that access to the PCI bus has been granted to the

CS5530. The CS5530 then issues a grant to the DMA

controller. This mechanism prevents any deadlock situa-

tions across the bridge. Once granted the PCI bus, the

ISA master or DMA transfer commences.

If an ISA master executes an I/O access, that cycle

remains on the ISA bus and is not forwarded to the PCI

bus. The CS5530 performs only single transfers on the

PCI bus for legacy DMA cycles.

Table 3-2. PCI Command Register

Bit

Description

F0 Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:10

Reserved: Set to 0.

Fast Back-to-Back Enable (Read Only): This function is not supported when the CS5530 is a master. It is always dis-

abled (always reads 0).

SERR#: Allow SERR# assertion on detection of special errors: 0 = Disable (Default);1 =Enable.

Wait Cycle Control (Read Only): This function is not supported in the CS5530. It is always disabled

(always reads 0).

Parity Error: Allow the CS5530 to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when

a parity error is detected: 0 = Disable (Default); 1 = Enable.

VGA Palette Snoop Enable (Read Only): This function is not supported in the CS5530. It is always disabled (always

reads 0).

Memory Write and Invalidate: Allow the CS5530 to do memory write and invalidate cycles, if the PCI Cache Line Regis-

ter (F0 Index 0Ch) is set to 16 bytes (04h). 0 = Disable (Default); 1 = Enable.

Special Cycles: Allow the CS5530 to respond to special cycles: 0 = Disable; 1 = Enable (Default).

This bit must be enabled to allow the CPU Warm Reset internal signal to be triggered from a CPU Shutdown cycle.

Bus Master: Allow the CS5530 bus mastering capabilities: 0 = Disable; 1 = Enable (Default).

This bit must be set to 1.

Memory Space: Allow the CS5530 to respond to memory cycles from the PCI bus:

0 = Disable; 1 = Enable (Default).

I/O Space: Allow the CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable (Default).

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