CS5530 datasheet(89/241 Pages) NSC

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Functional Description (Continued)

3.5.2.3

ISA Bus Data Steering

TheCS5530performsall of the requireddatasteering

from SD[7:0] to SD[15:0] during normal 8-bit ISA cycles,

as well as during DMA and ISA master cycles. It handles

data transfers between the 32-bit PCI data bus and the

ISA bus. 8/16-bit devices can reside on the ISA bus. Vari-

ous PC-compatible I/O registers, DMA controller registers,

interrupt controller registers, and counter/timer registers

lie on the on-chip I/O data bus. Either the PCI bus master

or theDMA controllers canbecomethe busowner.

When the PCI bus master is the bus owner, the CS5530

data steering logic provides data conversion necessary

for 8/16/32-bit transfers to and from 8/16-bit devices on

either the ISA bus or the 8-bit registers on the on-chip I/O

data bus. When PCI data bus drivers of the CS5530 are

tristated, data transfers between the PCI bus master and

PCI bus devices are handled directly via the PCI data bus.

When the DMA requestor is the bus owner, the CS5530

allows 8/16-bit data transfer between the ISA bus and the

PCI data bus.

3.5.2.4

I/O Recovery Delays

In normal operation, the CS5530 inserts a delay between

back-to-back ISA I/O cycles that originate on the PCI bus.

The default delay is four ISACLK cycles. Thus, the second

of consecutive I/O cycles is held in the ISA bus controller

until this delay count has expired. The delay is measured

between the rising edge of IOR#/IOW# and the falling

edge of BALE. This delay can be adjusted to a greater

delay through the ISA I/O Recovery Control Register (F0

Index 51h, see Table 3-37).

Note:

This delay is not inserted for a 16-bit ISA I/O

access that is split into two 8-bit I/O accesses.

Table 3-37. I/O Recovery Programming Register

Bit

Description

F0 Index 51h

ISA I/O Recovery Control Register (R/W)

Reset Value = 44h

7:4

8-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This

count is in addition to a preset one-clock delay built into the controller.

0000 = 1 PCI clock

0100 = 5 PCI clocks

1000 = 9 PCI clocks

1100 = 13 PCI clocks

0001 = 2 PCI clocks

0101 = 6 PCI clocks

1001 = 10 PCI clocks

1101 = 14 PCI clocks

0010 = 3 PCI clocks

0110 = 7 PCI clocks

1010 = 11 PCI clocks

1110 = 15 PCI clocks

0011 = 4 PCI clocks

0111 = 8 PCI clocks

1011 = 12 PCI clocks

1111 = 16 PCI clocks

3:0

16-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This