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Signal Definitions (Continued)

2.2.11 Display Interface

Signal Name

No.

Type

Description

Pixel Port

PCLK

A13

Pixel Clock

This clock is used to sample data on the PIXEL input port. It runs at the

graphics DOT clock (DCLK) rate.

PIXEL[23:0]

Refer

Table

2-3

Pixel Data Port

This is the input pixel data from the processor’s display controller. If

F4BAR+Memory Offset 00h[29] is reset, the data is sent in RGB 8:8:8 for-

mat. Otherwise, the pixel data is sent in RGB 5:6:5 format which has been

dithered by the processor. The other eight bits are used in conjunction

with VID_DATA[7:0] to provide 16-bit video data. This bus is sampled by

the PCLK input.

ENA_DISP

Display Enable Input

This signal qualifies active data on the pixel input port. It is used to qualify

active pixel data for all display modes and configurations and is not spe-

cific to flat panel display.

Display CRT

HSYNC

Horizontal Sync Input

This is the CRT horizontal sync input from the processor’s display control-

ler. It is used to indicate the start of a new video line. This signal is pipe-

lined for the appropriate number of clock stages to remain in sync with the

pixel data. A separate output (HSYNC_OUT) is provided to re-drive the

CRT and flat panel interfaces.

HSYNC_OUT

Horizontal Sync Output

This is the horizontal sync output to the CRT. It represents a delayed ver-

sion of the input horizontal sync signal with the appropriate pipeline delay

relative to the pixel data. The pipeline delay and polarity of this signal are

programmable.

VSYNC

Vertical Sync Input

This is the CRT vertical sync input from the processor’s display controller.

It is used to indicate the start of a new frame. This signal is pipelined for

the appropriate number of clock stages to remain in sync with the pixel

data. A separate output (VSYNC_OUT) is provided to re-drive the CRT

and flat panel interfaces.

VSYNC_OUT

Vertical Sync Output

This is the vertical sync output to the CRT. It represents a delayed version

of the input vertical sync signal with the appropriate pipeline delay relative

to the pixel data. The pipeline delay and polarity of this signal are pro-

grammable.

DDC_SCL

DDC Serial Clock

This is the serial clock for the VESA Display Data Channel interface. It is

used for monitor communications. The DDC2B standard is supported by

this interface.

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