CS5530 datasheet(55/241 Pages) NSC

55 / 241 page

Revision 4.1

www.national.com

Functional Description (Continued)

3.4.2

CPU Power Management

The three greatest power consumers in a system are the

display, the hard drive, and the CPU. The power manage-

ment of the first two is relatively straightforward and is dis-

cussed in Section 3.4.3 “Peripheral Power Management”

on page 60.

APM,ifavailable,isusedprimarily by CPUpower man-

agement since the operating system is most capable of

reporting the Idle condition. Additional resources provided

by the CS5530 supplement APM by monitoring external

activity and power managing the CPU based on the sys-

tem demands. The two processes for power managing the

CPU are Suspend Modulation and 3 Volt Suspend.

3.4.2.1

Suspend Modulation

Suspend Modulation works by asserting and de-asserting

the SUSP# pin to the CPU for configurable durations.

When the SUSP# pin is asserted to the processor, the

processor enters an Idle state during which time the

power consumption is significantly reduced. Even though

the PCI clock is still running, the processor stops clocks to

its core when SUSP# is asserted. By modulating the

SUSP# pin, a reduced frequency of operation is achieved.

The Suspend Modulation feature works by assuming that

the processor is idle unless external activity indicates oth-

erwise. This approach effectively slows down the proces-

sor until external activity indicates a need to run at full

speed,

thereby

reducing

power

consumption.

This

approach is the opposite of that taken by most power

management schemes in the industry, which run the sys-

tem at full speed until a period of inactivity is detected,

and then slows down. Suspend Modulation, the more

aggressive approach, yields lower power consumption.

Suspend Modulation serves as the primary CPU power

management mechanism when APM is not present. It

also acts as a backup for situations where APM does not

correctly detect an Idle condition in the system.

In order to provide high-speed performance when

needed, the SUSP# pin modulation is temporarily dis-

abled any time system activity is detected. When this hap-

pens, the processor is “instantly” converted to full speed

for a programmed duration. System activities in the

CS5530 are asserted as: any unmasked IRQ, accessing

Port 061h, any asserted SMI, and/or accessing the video

port.

Since the graphics controller is integrated in the GXLV

processor, the indication of video activity is sent to the

CS5530 via the serial link (see Section 3.1.2 “PSERIAL

Pin Interface” on page 44 for more information on serial

link) and is automatically decoded. Video activity is

defined as any access to the VGA register space, the

VGA frame buffer, the graphics accelerator control regis-

ters and the configured graphics frame buffer.

The automatic speedup events (video and IRQ) for Sus-

pend Modulation should be used together with software-

controlled speedup registers for major I/O events such as

any access to the floppy disk controller, hard disk drive, or

parallel/serial ports, since these are indications of major

system activities. When major I/O events occur, Suspend

Modulation should be temporarily disabled using the pro-

cedures described in the Power Management Registers in

the following subsections.

If a bus master (Ultra DMA/33, Audio, USB) request

(REQ#) occurs, the processor automatically deasserts

SUSPA# and grants (GNT#) the bus to the requesting bus

master. When the bus master deasserts REQ#, SUSPA#

reasserts. This does not directly affect the Suspend Mod-

ulation programming.

Table 3-12. APM Support Registers

Bit

Description

F0 Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0]

= 0), a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state.

The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt

condition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted

after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4]

will be invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are

the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external

SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to

wake-up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active,

internal SMI events are also Resume events.

F0 Index D0h

Software SMI Register (WO)

Reset Value = 00h

7:0

Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows

software entry into SMM via normal bus access instructions.

CS5530 数据表(PDF) 55 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 55 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载