CS5530 datasheet(47/241 Pages) NSC

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Functional Description (Continued)

3.2.3

Special Bus Cycles–Shutdown/Halt

The PCI interface does not pass Special Bus Cycles to

the ISA interface, since special cycles by definition have

no destination. However, the PCI interface monitors the

PCI bus for Shutdown and Halt Special Bus Cycles.

Upon detection of a Shutdown Special Bus Cycle, a

WM_RST SMI is generated after a delay of three PCI

clock cycles. PCI Shutdown Special Cycles are detected

when C/BE[3:0]# = 0001 during the address phase and

AD[31:0] = xxxx0000h during the data phase. C/BE[3:0]#

are also properly asserted during the data phase.

Upon detection of a Halt Special Bus Cycle, the CS5530

completes the cycle by asserting TRDY#. PCI Halt Spe-

cial Bus Cycles are detected when CBE[3:0]# = 0001 dur-

ing the address phase and AD[31:0] = xxxx0001h during

the data phase of a Halt cycle. CBE[3:0]# are also prop-

erly asserted during the data phase.

3.2.4

PCI Bus Parity

When the CS5530 is the PCI initiator, it generates

address parity for read and write cycles. It checks data

parity for read cycles and it generates data parity for write

cycles. The PAR signal is an even-parity bit that is calcu-

lated across 36 bits of AD[31:0] plus C/BE[3:0]#.

By default, the CS5530 does not report parity errors. How-

ever, the CS5530 detects parity errors during the data

phase if F0 Index 04h[6] is set to 1. If enabled and a data

parity error is detected, the CS5530 asserts PERR#. It

also asserts SERR# if F0 Index 41h[5] is set to 1. This

allows NMI generation.

The CS5530 also detects parity errors during the address

phase if F0 Index 04h[6] is set. When parity errors are

detected during the address phase, SERR# is asserted

internally. Parity errors are reported to the CPU by

enabling the SERR# source in I/O Port 061h (Port B) con-

trol register. The CS5530 sets the corresponding error bits

in the PCI Status Register (F0 Index 06h[15:14]). Table 3-

5 shows these programming bits.

If the CS5530 is the PCI master for a cycle and detects

PERR# asserted, it generates SERR# internally.

Table 3-5. PERR#/SERR# Associated Register Bits

Bit

Description

F0 Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

Parity Error: Allow the CS5530 to check for parity errors on PCI cycles for which it is a target, and to assert PERR# when

a parity error is detected: 0 = Disable (Default); 1 = Enable.

F0 Index 06h-07h

PCI Status Register (R/W)

Reset Value = 0280h

Detected Parity Error: This bit is set whenever a parity error is detected.

Write 1 to clear.

Signaled System Error: This bit is set whenever the CS5530 asserts SERR# active.

Write 1 to clear.

F0 Index 41h

PCI Function Control Register 2 (R/W)

Reset Value = 10h

PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530 (allows

PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 = Enable.

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