CS5530 datasheet(90/241 Pages) NSC

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Functional Description (Continued)

3.5.2.5

ISA DMA

DMA transfers occur between ISA I/O peripherals and

system memory. The data width can be either 8 or 16 bits.

Out of the seven DMA channels available, four are used

for 8-bit transfers while the remaining three are used for

16-bit transfers. One BYTE or WORD is transferred in

each DMA cycle.

Note:

The CS5530 does not support DMA transfers to

ISA memory.

The ISA DMA device initiates a DMA request by asserting

oneofthe DRQ[7:5,3:0]signals.When theCS5530

receives this request, it sends a bus grant request to the

PCI arbiter. After the PCI bus has been granted, the

respective DACK#is drivenactive.

The CS5530 generates PCI memory read or write cycles

in response to a DMA cycle. Figures 3-12 and 3-13 are

examples of DMA memory read and memory write cycles.

Upon detection of the DMA controller’s MEMR# or

MEMW#active, theCS5530startsthe PCIcycle, asserts

FRAME#, and negates an internal IOCHRDY. This

assures the DMA cycle does not complete before the PCI

cycle has provided or accepted the data. IOCHRDY is

internally asserted when IRDY# and TRDY# are sampled

active.

Figure 3-12. ISA DMA Read from PCI Memory

Figure 3-13. ISA DMA Write To PCI Memory

PCICLK

ISACLK

MEMR#

IOW#

FRAME#

AD[31:0]

IRDY#

TRDY#

SD[15:0]

IOCHRDY

PCICLK

ISACLK

MEMW#

IOR#

FRAME#

AD[31:0]

IRDY#

TRDY#

SD[15:0]

IOCHRDY

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