CS5530 datasheet(27/241 Pages) NSC

27 / 241 page

Revision 4.1

www.national.com

Signal Definitions (Continued)

2.2.5

ISA Bus Interface

Signal Name

No.

Type

Description

SA_LATCH/

SA_DIR

AD15

Limited ISA Mode: System Address Latch

This signal is used to latch the destination address, which is multiplexed

on bits [15:0] of the SA/SD bus.

ISA Master Mode: System Address Direction

Controls the direction of the external 5.0V tolerant transceiver on bits

[15:0] of the SA bus. When low, the SA bus is driven out. When high, the

SA bus is driven into the CS5530 by the external transceiver.

SA_OE#/

FP_DATA16

Limited ISA Mode: Flat Panel Data Port Line 16

Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def-

inition.

ISA Master Mode: System Address Transceiver Output Enable

Enables the external transceiver on bits [15:0] of the SA bus.

MASTER#/

FP_DATA17

Limited ISA Mode: Flat Panel Data Port Line 17

Refer to Section 2.2.11 “Display Interface” on page 34 for this signal’s def-

inition.

ISA Master Mode: Master

The MASTER# input asserted indicates an ISA bus master is driving the

ISA bus.

SA23/GPIO7

AF23

I/O

5VT

Limited ISA Mode: System Address Bus Lines 23 through 20 or

General Purpose I/Os 7 through 4

These pins can function either as the upper four bits of the SA bus or as

general purpose I/Os. Programming is done through F0 Index 43h, bits 6

and 2.

Refer to Section 2.2.9 “Game Port and General Purpose I/O Interface” on

page 32 for further details when used as GPIOs.

SA22/GPIO6

AE23

SA21/GPIO5

AC21

SA20/GPIO4

AD22

ISA Master Mode: System Address Bus Lines 23 through 20

The pins function only as the four MSB (most significant bits) of the SA

bus.

SA[19:16]

AD10,

AE11,

AF12,

AD11

I/O

5VT

System Address Bus Lines 19 through 16

Refer to SA[15:0] signal description.

SA[15:0]/SD[15:0]

Refer

Table

2-3

I/O

5VT

Limited ISA Mode: System Address Bus / System Data Bus

This bus carries both the addresses and data for all ISA cycles. Initially,

the address is placed on the bus and then SA_LATCH is asserted for

external latches to latch the address. At some time later, the data is put on

the bus, for a read, or the bus direction is changed to an input, for a write.

Pins designated as SA/SD[15:0] are internally connected to a 20-kohm

pull-up resistor.

ISA Master Mode: System Data Bus

These pins perform only as SD[15:0] and pins FP_DATA[15:0] take on the

functions of SA[15:0].

Pins designated as SA/SD[15:0] are internally connected to a 20-kohm

pull-up resistor.

CS5530 数据表(PDF) 27 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 27 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载