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CS5530 数据表(PDF) 13 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5530
功能描述  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5530 数据表(HTML) 13 Page - National Semiconductor (TI)

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Revision 4.1
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Signal Definitions (Continued)
2.1
PIN ASSIGNMENTS
The tables in this section use several common abbrevia-
tions. Table 2-1 lists the mnemonics and their meanings.
Figure 2-2 shows the pin assignment for the CS5530 with
Tables 2-2 and 2-3 listing the pin assignments sorted by
terminal number and alphabetically by signal name,
respectively.
In Section 2.2 “Signal Descriptions” a description of each
signal within its associated functional group is provided.
In the signal definitions, references to F0-F4, F1BAR,
F2BAR, F3BAR, F4BAR, and PCIUSB are made. These
terms relate to designated register spaces. Refer to Table
4-1 "PCI Configuration Address Register (0CF8h)" on
page 138 for details regarding these register spaces and
their access mechanisms.
Table 2-1. Pin Type Definitions
Mnemonic
Definition
5VT
Buffer is 5V tolerant
I
Input pin
I/O
Bidirectional pin
IBUF
Input buffer
OOutput
OD
Open-drain output structure that
allows multiple devices to share the
pin in a wired-OR configuration
PU
Pull-up resistor
PD
Pull-down resistor
smt
Schmitt Trigger
t/s
Tri-state signal
VDD (PWR)
Power pin
VSS (GND)
Ground pin
#
The "#" symbol at the end of a signal
name indicates that the active, or
asserted state occurs when the signal
is at a low voltage level. When "#" is
not present after the signal name, the
signal is asserted when at a high volt-
age level.



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