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数据搜索系统，热门电子元器件搜索 |
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CS5530 数据表(PDF) 85 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 85 Page - National Semiconductor (TI) |
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85 / 241 page  Revision 4.1 85 www.national.com Functional Description (Continued) 3.5.2 ISA Bus Interface The ISA bus controller issues multiple ISA cycles to sat- isfy PCI transactions that are larger than 16 bits. A full 32- bit read or write results in two 16-bit ISA transactions or four 8-bit ISA transactions. The ISA controller gathers the data from multiple ISA read cycles and returns TRDY# only after all of the data can be presented to the PCI bus at the same time. SA[23:0] are a concatenation of ISA LA[23:17] and SA[19:0] and perform equivalent functionality at a reduced pin count. Figure 3-8 shows the relationship between a PCI cycle and the corresponding ISA cycle generated. Figure 3-8. Non-Posted PCI-to-ISA Access PCI_CLK ISACLK FRAME# IRDY# TRDY# AD[31:0] (Read) IOR#/IOW# AD[31:0] (Write) BALE STOP# MEMR#/MEMW# |
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