CS5530 datasheet(100/241 Pages) NSC

100 / 241 page

www.national.com

100

Revision 4.1

Functional Description (Continued)

3.5.5

I/O Ports 092h and 061h System Control

The CS5530 supports control functions of I/O Ports 092h

(Port A) and 061h (Port B) for PS/2 compatibility. I/O Port

092h allows a fast assertion of the A20M# or CPU_RST.

I/O Port 061h controls NMI generation and reports system

status. Table 3-47 shows these register bit formats.

The CS5530 does not use a pin to control A20 Mask

when used together with a GXLV processor. Instead, it

generates an SMI for every internal change of the A20M#

state and the SMI handler sets the A20M# state inside the

CPU. This method is used for both the Port 092h (PS/2)

and Port 061h (keyboard) methods of controlling A20M#.

Table 3-47. I/O Ports 061h and 092h

Bit

Description

I/O Port 061h

Port B Control Register (R/W)

Reset Value = 00x01100b

PERR#/SERR# Status (Read Only): Was a PCI bus error (PERR#/ SERR#) asserted by a PCI device or by CS5530?

0= No; 1 = Yes.

This bit can only be set if ERR_EN is set 0. This bit is set 0 after a write to ERR_EN with a 1 or after reset.

IOCHK# Status (Read Only): Is an I/O device reporting an error to the CS5530? 0 = No; 1 = Yes.

This bit can only be set if IOCHK_EN is set 0. This bit is set 0 after a write to IOCHK_EN with a 1 or after reset.

PIT OUT2 State (Read Only): This bit reflects the current status of the PIT Timer2-OUT2.

Toggle (Read Only): This bit toggles on every falling edge of Counter 1 (OUT1).

IOCHK Enable:

0 = Generates an NMI if IOCHK# is driven low by an I/O device to report an error. Note that NMI is under SMI control.

1 = Ignores the IOCHK# input signal and does not generate NMI.

PERR#/ SERR# Enable: Generate an NMI if PERR#/ SERR# is driven active to report an error:

0 = Enable; 1 = Disable

PIT Counter2 (SPKR): 0 = Forces Counter 2 output (OUT2) to zero. 1 = Allows Counter 2 output (OUT2) to pass to the

speaker

PIT Counter2 Enable: 0 = Sets GATE2 input low. 1 = Sets GATE2 input high.

I/O Port 092h

Port A Control Register (R/W)

Reset Value = 02h

7:2

Reserved: Set to 0.

A20M# SMI Assertion: Assert A20# SMI: 0 = Enable; 1 = Disable.

Fast CPU Reset: WM_RST SMI is asserted to the BIOS: 0 = Disable; 1 = Enable.

This bit must be cleared before the generation of another reset.

CS5530 数据表(PDF) 100 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 100 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载