CS5530 datasheet(102/241 Pages) NSC

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102

Revision 4.1

Functional Description (Continued)

3.5.6

Keyboard Interface Function

The CS5530 actively decodes the keyboard controller I/O

Ports 060h and 064h, and generate an ISA I/O cycle with

KBROMCS# asserted. Access to I/O Ports 062h and

066h must be enabled for KBROMCS# to be asserted.

The CS5530 also actively decodes the keyboard control-

ler I/O Ports 062h and 066h if F0 Index 5Bh[7] is set. Key-

board positive decoding can be disabled if F0 Index

5Ah[1] is cleared. Table 3-49 shows these two decoding

bits.

Table 3-50 lists the standard keyboard control I/O regis-

ters and their bit formats.

Table 3-49. Decode Control Registers

Bit

Description

F0 Index 5Ah

Decode Control Register 1 (R/W)

Reset Value = 03h

Keyboard Controller Positive Decode: Selects positive or subtractive decoding for accesses to I/O Port 060h and 064h

(and 062h/066h if enabled): 0 = Subtractive; 1 = Positive.

Note: Positive decoding by the CS5530 speeds up the I/O cycle time. These I/O Ports do not exist in the CS5530. It is assumed that

if positive decode is enabled, the port exists on the ISA bus.

F0 Index 5Bh

Decode Control Register 2 (R/W)

Reset Value = 20h

Keyboard I/O Port 062h/066h Decode: This alternate port to the keyboard controller is provided in support of the

8051SL notebook keyboard controller mailbox: 0 = Disable; 1 = Enable.

Note: Positive decoding by the CS5530 speeds up the I/O cycle time. The Keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in

the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus.

Table 3-50. External Keyboard Controller Registers

Bit

Description

I/O Port 060h (R/W)

External Keyboard Controller Data Register

Keyboard Controller Data Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and reset fea-

tures are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes to this

port assert the A20M# pin or cause a warm CPU reset.

I/O Port 062h (R/W)

External Keyboard Controller Mailbox Register

Keyboard Controller Mailbox Register: Accesses to this port asserts KBROMCS# if the I/O Port 062h/066h decode is enabled

through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).

I/O Port 064h (R/W)

External Keyboard Controller Command Register

Keyboard Controller Command Register: All accesses to this port are passed to the ISA bus. If the fast keyboard gate A20 and

reset features are enabled through bit 7 of the ROM/AT Logic Control Register (F0 Index 52h[7]), the respective sequences of writes

to this port assert the A20M# pin or cause a warm CPU reset.

I/O Port 066h (R/W)

External Keyboard Controller Mailbox Register

Keyboard Controller Mailbox Register: Accesses to this port assert KBROMCS# if the I/O Port 062h/066h decode is enabled

through bit 7 of the Decode Control Register 2 (F0 Index 5Bh[7]).

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