CS5530 datasheet(103/241 Pages) NSC

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Functional Description (Continued)

3.5.6.1

Fast Keyboard Gate Address 20 and CPU

Reset

The CS5530 monitors the keyboard I/O Ports 064h and

060h for the fast keyboard A20M# and CPU reset control

sequences. If a write to I/O Port 060h[1] = 1 after a write

takes place to I/O Port 064h with data of D1h, then the

CS5530 asserts the A20M# signal. A20M# remains

asserted until cleared by:

(1) a write to bit 1 of I/O Port 092h,

(2) a CPU reset of some kind, or

(3) write to I/O Port 060h[1] = 0 after a write takes place

to I/O Port 064h with data of D1h,

The CS5530 also monitors the keyboard ports for the

CPU reset control sequence. If a write to I/O Port 060h

with data bit 0 set occurs after a write to I/O Port 064h

with data of D1h, the CS5530 asserts a WM_RST SMI.

The fast keyboard A20M# and CPU reset can be disabled

through F0 Index 52h[7]. By default, bit 7 is cleared, and

the fast keyboard A20M# and CPU reset monitor logic is

active. If bit 7 is clear, the CS5530 forwards the com-

mands to the keyboard controller.

By default, the CS5530 forces the deassertion of A20M#

during a warm reset. This action may be disabled if F0

Index 52h[4] is cleared.

Table 3-51. A20 Associated Programming Bits

Bit

Description

F0 Index 52h

ROM/AT Logic Control Register (R/W)

Reset Value = F8h

Snoop Fast Keyboard Gate A20 and Fast Reset: Enables the snoop logic associated with keyboard commands for

A20 Mask and Reset: 0 = Disable; 1 = Enable (snooping).

If disabled, the keyboard controller handles the commands.

Enable A20M# Deassertion on Warm Reset: Force A20M# high during a Warm Reset (guarantees that A20M# is deas-

serted regardless of the state of A20): 0 = Disable; 1 = Enable.

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