CS5530 datasheet(29/241 Pages) NSC

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Signal Definitions (Continued)

IOCHRDY

AF11

I/O

5VT

I/O Channel Ready

IOCHRDY deasserted indicates that an ISA slave requires additional wait

states.

When the CS5530 is an ISA slave, IOCHRDY is an output indicating addi-

tional wait states are required.

ZEROWS#

AF10

5VT

Zero Wait States

ZEROWS# asserted indicates that an ISA 8- or 16-bit memory slave can

shorten the current cycle. The CS5530 samples this signal in the phase

after BALE is asserted. If asserted, it shortens 8-bit cycles to three

ISACLKs and 16-bit cycles to two ISACLKs.

IOCS16#

AF16

5VT

I/O Chip Select 16

IOCS16# is asserted by 16-bit ISA I/O devices based on an asynchronous

decode of SA[15:0] to indicate that SD[15:0] will be used to transfer data.

Note:

8-bit ISA I/O devices only use SD[7:0].

IOR#

AE12

I/O

5VT

I/O Read

IOR# is asserted to request an ISA I/O slave to drive data onto the data

bus.

This pin is internally connected to a 20-kohm pull-up resistor.

IOW#

AC11

I/O

5VT

I/O Write

IOW# is asserted to request an ISA I/O slave to accept data from the data

bus.

This pin is internally connected to a 20-kohm pull-up resistor.

MEMCS16#

AC15

I/O

5VT

Memory Chip Select 16

MEMCS16# is asserted by 16-bit ISA memory devices based on an asyn-

chronous decode of SA[23:17] to indicate that SD[15:0] will be used to

transfer data.

Note: 8-bit ISA memory devices only use SD[7:0].

MEMR#

AE19

I/O

5VT

Memory Read

MEMR# is asserted for any memory read accesses. It enables 16-bit

memory slaves to decode the memory address on SA[23:0].

This pin is internally connected to a 20-kohm pull-up resistor.

MEMW#

AF20

I/O

5VT

Memory Write

MEMW# is asserted for any memory write accesses. It enables 16-bit

memory slaves to decode the memory address on SA[23:0].

This pin is internally connected to a 20-kohm pull-up resistor.

AEN

AE8

Address Enable

AEN asserted indicates that a DMA transfer is in progress, informing I/O

devices to ignore the I/O cycle.

IRQ[15:14], [12:9],

[7:3], 1

Refer

Table

2-3

5VT

ISA Bus Interrupt Request

IRQ inputs indicate ISA devices or other devices requesting a CPU inter-

rupt service.

IRQ8#

AE14

5VT

Real-Time Clock Interrupt

IRQ8# is the (active-low) interrupt that can come from the external RTC

chip and indicates a date/time update has completed.

2.2.5

ISA Bus Interface (Continued)

Signal Name

No.

Type

Description

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