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数据搜索系统，热门电子元器件搜索 |
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CS5530 数据表(PDF) 31 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 31 Page - National Semiconductor (TI) |
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31 / 241 page  Revision 4.1 31 www.national.com Signal Definitions (Continued) 2.2.7 IDE Interface Signal Name Pin No. Type Description IDE_RST# W25 O IDE Reset This signal resets all the devices that are attached to the IDE interface. IDE_ADDR[2:0] W24, U26, U25 O IDE Address Bits These address bits are used to access a register or data port in a device on the IDE bus. IDE_DATA[15:0] Refer to Table 2-3 I/O 5VT IDE Data Lines IDE_DATA[15:0] transfers data to/from the IDE devices. IDE_IOR0# R26 O IDE I/O Read for Channels 0 and 1 IDE_IOR0# is the read signal for Channel 0, and IDE_IOR1# is the read signal for Channel 1. Each signal is asserted on read accesses to the cor- responding IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — DMARDY0# and DMARDY1# Write Cycle — STROBE0 and STROBE1 IDE_IOR1# R25 O IDE_IOW0# R24 O IDE I/O Write for Channels 0 and 1 IDE_IOW0# is the write signal for Channel 0, and IDE_IOW1# is the read signal for Channel 1. Each signal is asserted on write accesses to corre- sponding the IDE port addresses. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — STOP0 and STOP1 WriteCycle— STOP0and STOP1 IDE_IOW1# T25 O IDE_CS0# V26 O IDE Chip Selects The chip select signals are used to select the command block registers in an IDE device. IDE_CS1# Y26 O IDE_IORDY0 AD25 I 5VT I/O Ready Channels 0 and 1 When deasserted, these signals extend the transfer cycle of any host reg- ister access when the device is not ready to respond to the data transfer request. When in Ultra DMA/33 mode, these signals are redefined: Read Cycle — STROBE0 and STROBE1 WriteCycle— DMARDY0# andDMARDY1# IDE_IORDY1 AE26 I 5VT IDE_DREQ0 AD26 I 5VT DMA Request Channels 0 and 1 The DREQ is used to request a DMA transfer from the CS5530. The direction of the transfers are determined by the IDE_IOR/IOW signals. IDE_DREQ1 AC24 I 5VT IDE_DACK0# T26 O DMA Acknowledge Channels 0 and 1 The DACK# acknowledges the DREQ request to initiate DMA transfers. IDE_DACK1# T24 O |
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